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Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 8124496 | Cable connector assembly with improved printed circuit board A cable connector assembly (100) comprises a mating member (3) assembled with a plurality of contacts (33, 34), a printed circuit board (2), a cable (7) having a plurality of wires (71) and a strain relief portion (72... | 02/28/2012 |
| 7709350 | Method for manufacturing a semiconductor elemental device A method for manufacturing a semiconductor elemental device including an SOI structure in which an SOI layer is laminated, includes the steps of setting transistor forming regions and a device isolation region to the SOI layer, forming a pad oxide film over the SOI ... | 05/04/2010 |
| 7429514 | Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a t... | 09/30/2008 |
| 7300834 | Methods of forming wells in semiconductor devices Disclosed herein are methods of forming a well in a semiconductor device, in which a well end point under a trench is formed deeper than other area by well implantation prior to trench filling and by which leakage current is minimized. In one example, the disclosed ... | 11/27/2007 |
| 7244644 | Undercut and residual spacer prevention for dual stressed layers Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer ov... | 07/17/2007 |
| 7244661 | Method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process i... | 07/17/2007 |
| 7235460 | Method of forming active and isolation areas with split active patterning A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on t... | 06/26/2007 |
| 7192840 | Semiconductor device fabrication method using oxygen ion implantation A method of fabricating a semiconductor device having a silicon layer disposed on an insulating film. Oxygen ions are implanted into selected parts of the silicon layer, which are then oxidized to form isolation regions dividing the silicon layer into a plurality of... | 03/20/2007 |
| 7187056 | Radiation hardened bipolar junction transistor A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is fo... | 03/06/2007 |
| 7170147 | Dissipative isolation frames for active microelectronic devices, and methods of making such dissipative isolation frames Microelectronic apparatus having protection against high frequency crosstalk radiation, comprising: a planar insulating substrate; an active semiconductor electronic device located over a first region of the insulating substrate; and a doped semiconductor located in... | 01/30/2007 |
| 7166232 | Method for producing a solid body including a microstructure According to a method for producing a solid body (1) including a microstructure (2), the surface of a substrate (3) is provided with a masking layer (6) that is impermeable to a substance to be applied. The substance is then incorporated ... | 01/23/2007 |
| 7157340 | Method of fabrication of semiconductor device A manufacturing method of a semiconductor device, the method including implanting impurity ions into a silicon layer and irradiating a pulsed light having a pulse width of 100 milliseconds or less and a rise time of 0.3 milliseconds or more onto the silicon layer th... | 01/02/2007 |
| 7071534 | Antifuse structure and method of use An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programmin... | 07/04/2006 |
| 7049676 | Semiconductor device having a shielding layer The semiconductor device includes a multilevel interconnection formed on a semiconductor substrate. The multilevel interconnection includes a plurality of wiring layers each of which is insulated by an insulating layer. A metal member is formed as a shielding film i... | 05/23/2006 |
| 7015111 | Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a t... | 03/21/2006 |
| 6965132 | Polycrystalline silicon emitter having an accurately controlled critical dimension According to a disclosed embodiment, an etch stop layer is fabricated on top of a base. An amorphous layer is then formed on top of the etch stop layer. An opening is then etched in the amorphous layer and the etch stop layer. The opening is etched with an opening w... | 11/15/2005 |
| 6949445 | Method of forming angled implant for trench isolation A trench isolation having a sidewall and bottom implanted region located within a substrate of a first conductivity type is disclosed. The sidewall and bottom implanted region is formed by an angled implant, a 90 degree implant, or a combination of an angled implant... | 09/27/2005 |
| 6924209 | Method for fabricating an integrated semiconductor component A method for the fabrication of an integrated semiconductor component, in which at least one isolation trench is formed, a first layer of a nonconductive material is applied by a nonconformal deposition method, and a second layer of a nonconductive material is appli... | 08/02/2005 |
| 6924185 | Fuse structure and method to form the same A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse e... | 08/02/2005 |
| 6909196 | Method and structures for reduced parasitic capacitance in integrated circuit metallizations A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal leve... | 06/21/2005 |
| 6909976 | Method for calculating threshold voltage of pocket implant MOSFET A threshold voltage model with an impurity concentration profile in a channel direction taken into account is provided in the pocket implant MOSFET. With penetration length of the implanted pocket in the channel direction and the maximum impurity concentration of th... | 06/21/2005 |
| 6861320 | Method of making starting material for chip fabrication comprising a buried silicon nitride layer The invention provides a method of making silicon-on-insulator SOI substrates with nitride buried insulator layer by implantation of molecular deuterated ammonia ions ND3+, instead of implanting nitrogen ions (N+, or N2 | 03/01/2005 |
| 6855618 | Radiation hardened semiconductor device A method for manufacturing a radiation hardened semiconductor device, having defined active region and isolation region. The isolation region containing an isolation material and active region containing a transition region between active and isolation region, somet... | 02/15/2005 |
| 6846722 | Method for isolating a hybrid device in an image sensor The present disclosure relates to a method for fabricating an image sensor capable of improving dark current characteristics. The method includes: forming sequentially a pad oxide layer and a pad nitride layer on a substrate and selectively removing a portion of the... | 01/25/2005 |
| 6790752 | Methods of controlling VSS implants on memory devices, and system for performing same The present invention is generally directed to various methods of controlling Vss implants on memory devices, and a system for performing same. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substr... | 09/14/2004 |
| 6746936 | Method for forming isolation film for semiconductor devices The present invention relates to a method for forming an isolation film for semiconductor devices. This method comprises the steps of: successively forming a first oxide film and a nitride film on a semiconductor substrate; patterning the nitride film and the first ... | 06/08/2004 |
| 6730569 | Field effect transistor with improved isolation structures An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from th... | 05/04/2004 |
| 6706638 | Method of forming opening in dielectric layer A method of forming openings in the dielectric layer. The method includes an ion implantation step to reduce a lateral etching in a chemical vapor etching step, and to provide a high etching selectivity ratio of the dielectric layer to a mask. The dry etching proces... | 03/16/2004 |
| 6642120 | Semiconductor circuit A semiconductor circuit is provided which has a high breakdown voltage and is capable of outputting a large current. Field transistors (Q1, Q11) are cross-coupled. The gate of the first field transistor (Q1) and the drain of the second field transistor (Q... | 11/04/2003 |
| 6620704 | Method of fabricating low stress semiconductor devices with thermal oxide isolation A method is provided of fabricating a semiconductor device that includes forming a silicon oxide film on a semiconductor substrate. A silicon nitrite film may be formed on the silicon oxide film. A portion of the silicon nitrite film and the silicon oxide... | 09/16/2003 |
| 6583018 | Method of ion implantation An ion implantation method which can accurately control the effective dose amount even in ion implantation at a very low energy. This ion implantation method comprises the steps of carrying out preamorphization ion implantation for a semiconductor substra... | 06/24/2003 |
| 6583044 | Buried channel in a substrate and method of making same A buried channel and a method of fabricating a buried channel in a substrate including depositing a layer of masking material onto a surface of a substrate, etching a groove in the masking layer, etching a channel into the substrate through the groove, an... | 06/24/2003 |
| 6528390 | Process for fabricating a non-volatile memory device A method for fabricating a semiconductor structure includes growing regions of oxide on a first structure, to form bit-line regions; wherein said semiconductor structure includes a semiconducting substrate, a patterned ONO layer on said substrate, wherein... | 03/04/2003 |
| 6511893 | Radiation hardened semiconductor device A method for manufacturing a radiation hardened semiconductor device, having defined active region and isolation region. The isolation region containing an isolation material and active region containing a transition region between active and isolation re... | 01/28/2003 |
| 6482719 | Semiconductor field region implant methodology An MOS device is provided having a channel-stop implant placed between active regions and beneath field oxides. The channel-stop dopant material is a p-type material of atomic weight greater than boron, and preferably utilizes solely indium ions. The indi... | 11/19/2002 |
| 6426273 | Preprocessing method of metal film forming process A preprocessing method of a metal film formation process before formation of a BLM film on a resist film of a substrate to be processed, wherein the resist film of substrate to be processed is irradiated with plasma, utilizing a plasma processing apparatu... | 07/30/2002 |
| 6372607 | Photodiode structure A circuit that includes an isolation boundary formed to a depth in a substrate defining an active area of the substrate, a primary junction formed in the active area to a primary junction depth in the substrate to collect electron/hole pairs, and a second... | 04/16/2002 |
| 6358819 | Dual gate oxide process for deep submicron ICS An improved dual gate oxide process for dual-gated devices using oxygen ion implantation to vary the thickness of gate oxide layers. The desired layers are identified by photoresist layer patterning prior to an ion implantation. A subsequent heat treatmen... | 03/19/2002 |
| 6342431 | Method for eliminating transfer gate sacrificial oxide A method of forming a semiconductor device, includes forming a layer of oxide on a semiconductor substrate, forming a layer of silicon nitride on the oxide layer, forming isolation regions in the substrate using the oxide layer and the nitride layer, remo... | 01/29/2002 |
| 6340624 | Method of forming a circuitry isolation region within a semiconductive wafer A method of forming a circuitry isolation region within a semiconductive wafer comprises defining active area and isolation area over a semiconductive wafer. Semiconductive wafer material within the isolation area is wet etched using an etch chemistry whi... | 01/22/2002 |
