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| Number | Title | Issue Date |
| 8138060 | Wafer A wafer has a rare earth oxide layer disposed, typically sprayed, on a substrate. It is useful as a dummy wafer in a plasma etching or deposition system. ... | 03/20/2012 |
| 7888234 | Method for manufacturing a semiconductor body with a trench and semiconductor body with a trench A method for manufacturing a semiconductor body with a trench comprises the steps of etching the trench (11) in the semiconductor body (10) and forming a silicon oxide layer (12) on at least one side wall (14) of the trench (11) an... | 02/15/2011 |
| 7723206 | Photodiode A photodiode in which increased sensitivity and speed are balanced. The photodiode includes: a semiconductor substrate; a plurality of active regions formed on the substrate by selective epitaxial growth; and a comb electrode provided for each of the plurality of ac... | 05/25/2010 |
| 7601610 | Method for manufacturing a high integration density power MOS device A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; formi... | 10/13/2009 |
| 7413963 | Method of edge bevel rinse A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding th... | 08/19/2008 |
| 7402474 | Manufacturing method of semiconductor device A method of manufacturing a semiconductor device comprises the following steps: a step of depositing a silicon oxide film on the top surface of an epitaxial layer of the region where a high withstand voltage MOS transistor is formed; a step of subsequently depositin... | 07/22/2008 |
| 7317252 | Ohmic contact configuration A contact configuration has an ohmic contact between a metalization layer and a semiconductor body of monocrystalline semiconductor material. An amorphous semiconductor layer is formed between the metalization layer and the monocrystalline semiconductor body. The la... | 01/08/2008 |
| 7279398 | Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure.... | 10/09/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7271462 | Solid-state image sensing device A solid-state image sensing device that is free of kTC noise, can eliminate black smear and dark current, has a larger numerical aperture, and can eliminate the problem of insufficient area of the light-receiving portion. Photodiode PD is formed as the light-receivi... | 09/18/2007 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7259026 | Method and apparatus for processing organosiloxane film There is provided a method and apparatus for processing an organosiloxane film, which allow an inter-level insulating film with a low dielectric constant to be formed at a low heat process temperature. A semiconductor (10) with a coating film formed thereon i... | 08/21/2007 |
| 7244644 | Undercut and residual spacer prevention for dual stressed layers Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer ov... | 07/17/2007 |
| 7235460 | Method of forming active and isolation areas with split active patterning A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on t... | 06/26/2007 |
| 7220641 | Method for fabricating storage electrode of semiconductor device The present invention discloses improved method for manufacturing semiconductor device wherein a barrier layer is formed by thermally treating a hard mask polysilicon layer for protecting the sacrificial oxide film and the hard mask polysilicon film from damages. | 05/22/2007 |
| 7211295 | Silicon dioxide film forming method Disclosed herein is a silicon dioxide film forming method including: a reaction chamber heating step of heating a reaction chamber to a predetermined temperature, the reaction chamber containing an object to be processed; a gas pretreating step of energizing a proce... | 05/01/2007 |
| 7211779 | Pixel sensor with charge evacuation element and systems and methods for using such The pixel includes a reset element (350) used in relation to charging a light sensitive element (390). Further, the pixel includes a charge evacuation element (380) for dissipating charge build up about the reset element. Dissipation of the char... | 05/01/2007 |
| 7211863 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 05/01/2007 |
| 7202536 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 04/10/2007 |
| 7192855 | PECVD nitride film A method for forming a semiconductor device is provided. In accordance with the method, a substrate (103) is provided, and a dielectric material (123) is formed on the substrate through plasma enhanced chemical vapor deposition (PECVD). The PECVD is co... | 03/20/2007 |
| 7186630 | Deposition of amorphous silicon-containing films Chemical vapor deposition methods are used to deposit amorphous silicon-containing films over various substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, hig... | 03/06/2007 |
| 7180111 | Gate n-well/p-substrate photodiode A photodiode sensor structure includes a first dopant type substrate with a first surface and a second dopant type well region with a second surface. The second dopant type well region is formed in the first dopant type substrate such that the first surface and the ... | 02/20/2007 |
| 7176499 | Method of manufacturing a semiconductor light emitting device, semiconductor light emitting device, method of manufacturing a semiconductor device, semiconductor device, method of manufacturing a device, and device When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III-V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III-V compound semiconductor substrate ... | 02/13/2007 |
| 7163898 | Method for manufacturing semiconductor integrated circuit structures A method for manufacturing circuit structures integrated in a semiconductor substrate that includes regions, in particular isolation regions, includes the steps of:—depositing a conductive layer to be patterned onto the semiconductor substrate;—forming a first m... | 01/16/2007 |
| 7157297 | Method for fabrication of semiconductor device On a processed substrate having an engraved region as a depressed portion formed thereon, a nitride semiconductor thin film is laid. The sectional area occupied by the nitride semiconductor thin film filling the depressed portion is 0.8 times the sectional area of t... | 01/02/2007 |
| 7135738 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 11/14/2006 |
| 7132350 | Method for manufacturing a programmable eraseless memory A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in... | 11/07/2006 |
| 7102184 | Image device and photodiode structure The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first conductivity type with a first impurity concentration form a region surrounding at least part of the isolation re... | 09/05/2006 |
| 7101744 | Method for forming self-aligned, dual silicon nitride liner for CMOS devices A method for forming a self-aligned, dual silicon nitride liner for CMOS devices includes forming a first type nitride layer over a first polarity type device and a second polarity type device, and forming a topographic layer over the first type nitride layer. Porti... | 09/05/2006 |
| 7091524 | Semiconductor device and method for fabricating the same A semiconductor device has a substrate, a first Group III nitride semiconductor layer formed on the substrate, a first oxide layer formed in proximity to the upper portions of defects present in the first Group III nitride semiconductor layer, and a second Group III... | 08/15/2006 |
| 7091056 | Method of manufacturing a semiconductor light emitting device, semiconductor light emitting device, method of manufacturing a semiconductor device, semiconductor device, method of manufacturing a device, and device When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III–V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III–V compound semiconductor substr... | 08/15/2006 |
| 7071534 | Antifuse structure and method of use An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programmin... | 07/04/2006 |
| 7071115 | Use of multiple etching steps to reduce lateral etch undercut In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch att... | 07/04/2006 |
| 7056806 | Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure.... | 06/06/2006 |
| 7045437 | Method for fabricating shallow trenches A method of forming shallow trenches used, for example, in shallow trench isolation includes the steps of providing a p-type silicon substrate, forming a layer in the p-type silicon substrate, wherein the layer includes p-type silicon interposed between n-type silic... | 05/16/2006 |
| 6998665 | Magnetic memory device and manufacturing method therefor A magnetic memory device having a TMR element with high performance and high reliability, which can prevent oxidation or reduction of a tunnel dielectric layer in the TMR element. A nonvolatile magnetic memory device (1) includes a TMR element (13) con... | 02/14/2006 |
| 6962877 | Methods of preventing oxidation of barrier metal of semiconductor devices A method for preventing oxidation of a barrier metal layer of a semiconductor device is disclosed. The method includes the following steps. Ti/Ti(1-x)AlxN is deposited on the bottom and sidewalls of a via hole in a substrate by a plasma chemica... | 11/08/2005 |
| 6949448 | Local oxidation of silicon (LOCOS) method employing graded oxidation mask A method for forming a local oxidation of silicon (LOCOS) isolation region on a silicon substrate. A series of patterned graded oxidation mask layers formed of a material comprising silicon, oxygen and nitrogen is formed. The series of patterned graded oxidation mas... | 09/27/2005 |
| 6943039 | Method of etching ferroelectric layers Method of etching a ferroelectric layer includes etching an upper electrode and partially through a ferroelectric layer. A dielectric material is subsequently deposited upon the upper electrode and the partially etched ferroelectric layer. A second etch step complet... | 09/13/2005 |
| 6943088 | Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner roun... | 09/13/2005 |
