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| Number | Title | Issue Date |
| 7397070 | Self-aligned transistor In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor. ... | 07/08/2008 |
| 7361571 | Method for fabricating a trench isolation with spacers A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and ... | 04/22/2008 |
| 7358596 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 04/15/2008 |
| 7332387 | MOSFET structure and method of fabricating the same A MOSFET structure and a method of forming it are described. The thickness of a portion of the gate dielectric layer of the MOSFET structure adjacent to the drain region is increased to form a bird's beak structure. The gate-to-drain overlap capacitance is reduced b... | 02/19/2008 |
| 7329572 | Method of forming PIP capacitor A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor includes the steps of forming a lower electrode of a first polysilicon layer over a semiconductor substrate, forming a dielectric layer over the lower electrode, forming a second polysilicon lay... | 02/12/2008 |
| 7300850 | Method of forming a self-aligned transistor In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor. ... | 11/27/2007 |
| 7294578 | Use of a plasma source to form a layer during the formation of a semiconductor device A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further com... | 11/13/2007 |
| 7270763 | Anisotropic wet etching of silicon A silicon oxide film is formed on one principal surface of a silicon substrate by thermal oxidation, and thereafter, a silicon nitride film is formed on the silicon oxide film by CVD. A lamination layer of the silicon oxide film and silicon nitride film is selective... | 09/18/2007 |
| 7256113 | System for forming a semiconductor device and method thereof A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectr... | 08/14/2007 |
| 7247569 | Ultra-thin Si MOSFET device structure and method of manufacture The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a ... | 07/24/2007 |
| 7199020 | Nitridation of STI liner oxide for modulating inverse width effects in semiconductor devices A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor body (1308). Then, surfaces of the trench region are nitrided (1310) via a nitridation ... | 04/03/2007 |
| 7179584 | Exposure method and device for forming patterns on printed wiring board An optical exposure method and a device are used for forming patterns on a printed board wiring or semiconductor board. A single exposing region of a surface to be exposed is irradiated with a plurality of optical beams having different irradiating areas and differe... | 02/20/2007 |
| 7143445 | Information processing apparatus, information processing method, and program storage medium When a content is moved from a flash memory into a content database, a usage rule management program updates a variable seq-1, stored in a 0th defective block of a media defect list stored in the flash memory, to a new value seq-2. The usage rule manag... | 11/28/2006 |
| 7067391 | Method to form a metal silicide gate device A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the subst... | 06/27/2006 |
| 7057225 | Semiconductor memory circuitry Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. An integrated circuit includes a semiconductor die, a plurality of functional and operably addressable memory cells arrang... | 06/06/2006 |
| 7049206 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 05/23/2006 |
| 7009232 | Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in an 8-inch wafer Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6-inch, ... | 03/07/2006 |
| 6967369 | Semiconductor memory circuitry Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6-inch, ... | 11/22/2005 |
| 6955974 | Method for forming isolation layer of semiconductor device A method for forming an isolation layer of a semiconductor device, which comprises the steps of: a) sequentially forming a pad oxide layer and a pad nitride layer on a silicon substrate; b) etching the pad nitride layer, the pad oxide layer, and the silicon substrat... | 10/18/2005 |
| 6933215 | Process for doping a semiconductor body In a method of producing a doped semiconductor structure with a trench, it is possible to set the doping of the trench side walls independently from the doping of the trench bottom, and to set different doping concentrations of the individual trench side walls relat... | 08/23/2005 |
| 6917093 | Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallog... | 07/12/2005 |
| 6835640 | Method of forming a novel composite insulator spacer A method of defining composite insulator spacers on the sides of conductive gate structures, with reduced risk of semiconductor damage at end point of the composite insulator spacer definition procedure, has been developed. The method features initial deposition of ... | 12/28/2004 |
| 6720233 | Method of producing trench insulation in a substrate In a method of producing a trench insulation in a silicon substrate a first silicon-oxide layer is deposited on a front surface of a sequence of layers including the silicon substrate. Then the first silicon-oxide layer is structured so as to define a mask for a sub... | 04/13/2004 |
| 6682820 | Recession resistant coated ceramic part A recession resistant coated ceramic part. The ceramic part has a ceramic substrate and a recession resistant coating disposed on the substrate. The coating includes a plurality of layers diffusion bonded to each other and to the substrate respectively. T... | 01/27/2004 |
| 6661055 | Transistor in semiconductor devices The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which a voltage is applied apart from a gate electrode and forme... | 12/09/2003 |
| 6649488 | Method of shallow trench isolation After a trench is formed into a substrate, a polysilicon layer is formed on sidewalls and a bottom of the trench. A thermal oxidation is performed on the polysilicon layer such that a polysilicon oxide layer is formed thereon. Then, a portion of the polys... | 11/18/2003 |
| 6627516 | Method of fabricating a light receiving device A light receiving device includes a semiconductor substrate, a light absorbing layer provided on the semiconductor substrate, a window layer provided on the light absorbing layer, a wavelength filter provided on the window layer, and a diffusion region pr... | 09/30/2003 |
| 6613651 | Integrated circuit isolation system A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical propert... | 09/02/2003 |
| 6514816 | Method of fabricating a self-aligned shallow trench isolation A method of fabricating a self-aligned shallow trench isolation. A mask layer, two deep trenches and two internal electrodes of a capacitor are sequentially formed on a substrate. Two conductive layers are used to completely fill the two deep trenches. Th... | 02/04/2003 |
| 6482718 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device is provided which, even if device dimensions decrease, prevents degradation in the operating characteristics of semiconductor elements which are isolated from each other by an element isolation region in a ... | 11/19/2002 |
| 6444539 | Method for producing a shallow trench isolation filled with thermal oxide A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon ... | 09/03/2002 |
| 6319743 | Method of making thin film piezoresistive sensor Semiconductor piezoresistive sensors are formed by a process using selective laser activation of a doped semiconductor surface. The substrate is a flexible membrane such as a diaphragm or bellows. A layer of insulative dielectric material is first applied... | 11/20/2001 |
| 6306726 | Method of forming field oxide In one aspect, the invention encompasses a LOCOS process. A pad oxide layer is provided over a silicon-comprising substrate. A silicon nitride layer is provided over the pad oxide layer and patterned with the pad oxide layer to form masking blocks. The pa... | 10/23/2001 |
| 6255188 | Method of removing a polysilicon buffer using an etching selectivity solution A method of removing a polysilicon buffer in a method of forming a field oxide and an active area is disclosed herein that comprises the step of applying an etching selectivity solution to the polysilicon buffer to substantially remove the polysilicon buf... | 07/03/2001 |
| 6171930 | Device isolation structure and device isolation method for a semiconductor power integrated circuit The present invention relates to a device isolation structure and a device solation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region a... | 01/09/2001 |
| 6153482 | Method for fabricating LOCOS isolation having a planar surface which includes having the polish stop layer at a lower level than the LOCOS formation A method for fabricating LOCOS isolation having a planar surface. The method utilizes a polysilicon spacer to prevent bird beak. The method adds the steps of forming a polishing stop layer and removing said edge-protrusion portion of the local oxide by ch... | 11/28/2000 |
| 6133113 | Method of manufacturing shallow trench isolation A method of manufacturing shallow trench isolation comprising the steps of forming a pad oxide layer and a mask layer over a substrate, then patterning the pad oxide layer and the mask layer forming an opening in the substrate. Thereafter, insulating mate... | 10/17/2000 |
| 6121097 | Semiconductor device manufacturing method A polysilicon film is deposited in a trench formed in a silicon element substrate. The polysilicon film in the trench and on the silicon element substrate is anisotropically etched, so that the film remains on the side wall of the trench. The polysilicon ... | 09/19/2000 |
| 6114218 | Texturized polycrystalline silicon to aid field oxide formation A method of forming field oxide during the manufacture of a semiconductor device comprises the steps of providing a semiconductor wafer having a plurality of recesses or trenches therein. A layer of texturized polycrystalline silicon is formed within the ... | 09/05/2000 |
| 6093622 | Isolation method of semiconductor device using second pad oxide layer formed through chemical vapor deposition (CVD) An isolation method in the fabrication process of a semiconductor device is provided. The method forms an oxide layer as a buffer layer for reducing stress through chemical vapor deposition (CVD). By the method, a first pad oxide layer and a silicon nitri... | 07/25/2000 |
