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| Number | Title | Issue Date |
| 8178418 | Method for fabricating intra-device isolation structure A method for fabricating intra-device isolation structure is provided, including providing a semiconductor substrate with a mask layer formed thereover. A plurality of first trenches is formed in the semiconductor substrate and the mask layer. A first insulating lay... | 05/15/2012 |
| 7927969 | Cleaning of photolithography masks A method and an equipment for cleaning masks used for photolithography steps, including at least one step of thermal treatment under pumping at a pressure lower than the atmospheric pressure and at a temperature greater than the ambient temperature. ... | 04/19/2011 |
| 7892945 | Nanowire mesh device and method of fabricating same A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertic... | 02/22/2011 |
| 7413962 | Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is etched to form an opening defined by first and second cross-sectional sidewalls in the hard mask layer. I... | 08/19/2008 |
| 7407890 | Patterning sub-lithographic features with variable widths A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths ... | 08/05/2008 |
| 7393756 | Method for fabricating a trench isolation structure having a high aspect ratio A method for fabricating a trench isolation structure wherein a trench is formed in a silicon body and an oxide layer is formed in the trench. The silicon body is exposed at the bottom of the trench by means of an etching step, and silicon oxide is selectively grown... | 07/01/2008 |
| 7348267 | Flash memory and method of fabricating the same A method of fabricating a flash memory device produces a device that has a small cell area and yet a high coupling ratio. First, a basic structure is provided that includes a substrate, a field isolation film protruding from the substrate, and floating gates dispose... | 03/25/2008 |
| 7339252 | Semiconductor having thick dielectric regions A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second... | 03/04/2008 |
| 7314810 | Method for forming fine pattern of semiconductor device A method for forming fine patterns of a semiconductor device includes forming hard mask patterns over an underlying layer. A first organic film is formed over the hard mask patterns. A second organic film is formed over the first organic film. The second organic fil... | 01/01/2008 |
| 7273780 | Semiconductor device having box-shaped cylindrical storage nodes and fabrication method thereof A method of forming box-shaped cylindrical storage nodes includes forming an interlayer insulating layer on a semiconductor substrate. Buried contact plugs are formed to penetrate the interlayer insulating layer. A molding layer and a photoresist layer are then sequ... | 09/25/2007 |
| 7262127 | Method for Cu metallization of highly reliable dual damascene structures The present invention provides a method for forming a void-free copper damascene structure comprising a substrate having a conductive structure, a first dielectric layer on the substrate, a diffusion barrier layer on the first dielectric layer, and a second dielectr... | 08/28/2007 |
| 7256100 | Manufacturing method of semiconductor device having trench type element isolation A semiconductor substrate including a first region, a second region larger than the first region and an isolation region is provided. A mask layer is selectively formed on the first and second regions. A trench is formed on the isolation region. A first isolation ma... | 08/14/2007 |
| 7244644 | Undercut and residual spacer prevention for dual stressed layers Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer ov... | 07/17/2007 |
| 7238564 | Method of forming a shallow trench isolation structure A method and system for isolation trenches includes forming isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the tren... | 07/03/2007 |
| 7205207 | High performance strained CMOS devices A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si—SiO2 interfaces in a direction parallel to the direction of current flow and in a dire... | 04/17/2007 |
| 7192858 | Method of forming plug A method of producing a semiconductor device includes, in order to electrically connect a lower layer wiring and an upper layer wiring opposite to each other with an interlayer insulation film intervening between them, a step of forming a via-hole, which exposes the... | 03/20/2007 |
| 7183662 | Memory devices with memory cell transistors having gate sidewell spacers with different dielectric properties A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and secon... | 02/27/2007 |
| 7160671 | Method for argon plasma induced ultraviolet light curing step for increasing silicon-containing photoresist selectivity A method for increasing etching selectivity of a developed silicon-containing photoresist layer on a non-silicon containing photoresist layer on a substrate. The developed silicon-containing photoresist layer includes polymer chains containing silicon. Next, the dev... | 01/09/2007 |
| 7157350 | Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions t... | 01/02/2007 |
| 7148120 | Method of forming improved rounded corners in STI features A method for forming a shallow trench isolation (STI) structure with improved electrical isolation performance including providing a semiconductor substrate including an overlying silicon oxide layer on the semiconductor substrate and a hardmask layer on the silicon... | 12/12/2006 |
| 7122850 | Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor... | 10/17/2006 |
| 7094636 | Method of forming a conductive line A method of forming a conductive line includes forming conductive material received over a semiconductor substrate into a line having opposing sidewalls. Insulative material is deposited over the line, and is planarized. An insulating spacer forming layer is deposit... | 08/22/2006 |
| 7084502 | Microelectromechanical device and method for producing it A microelectromechanical device and a method for producing it having at least one layer on a substrate, in particular a thermoelectric layer on a substrate, the thermal expansion coefficient of the at least one layer and the thermal expansion coefficient of the subs... | 08/01/2006 |
| 7052972 | Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is etched to form an opening defined by first and second cross-sectional sidewalls in the hard mask layer. I... | 05/30/2006 |
| 7049206 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 05/23/2006 |
| 7049624 | Member and member manufacturing method A porous structure with high uniformity is provided even when evaluated at a high resolution (high evaluation standard) of several or several ten nm or less. By applying this porous structure to the manufacture of an SOI substrate, an SOI substrate which has an SOI ... | 05/23/2006 |
| 7045410 | Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is th... | 05/16/2006 |
| 7042062 | Device isolation structures of semiconductor devices and manufacturing methods thereof A device isolation structure of a semiconductor device may be a silicon wafer, a trench formed in the silicon wafer to have a predetermined depth, a first thermal oxide layer formed to an inner surface of the trench, a pad oxide layer formed on the silicon wafer, a ... | 05/09/2006 |
| 7041547 | Methods of forming polished material and methods of forming isolation regions In one aspect, the invention encompasses a method of forming a polished material. A substrate is provided and an elevational step is provided relative to the substrate. The elevational step has an uppermost surface. A material is formed beside the elevational step. ... | 05/09/2006 |
| 7041573 | Method for fabricating semiconductor device having trench isolation Disclosed is a method for fabricating a semiconductor device capable of preventing a depth of a plurality of moats M from getting deeper as preventing lowering a threshold voltage by forming a round shape of a top corner of a trench. Particularly, the method include... | 05/09/2006 |
| 7023069 | Method for forming thick dielectric regions using etched trenches A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second... | 04/04/2006 |
| 6995097 | Method for thermal nitridation and oxidation of semiconductor surface An embodiment of the instant invention is a method of forming a dielectric layer on a silicon-containing structure, the method comprising the steps of: providing a nitrogen-containing gas; heating the silicon-containing structure to an elevated temperature which is ... | 02/07/2006 |
| 6991994 | Method of forming rounded corner in trench A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxid... | 01/31/2006 |
| 6979878 | Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the ma... | 12/27/2005 |
| 6958276 | Method of manufacturing trench-type MOSFET In a method of manufacturing MOSFET devices, and particularly to the trench-type MOSFET devices, embodiments of the present invention provide methods of forming bottom oxide layers having uniform thickness on the bottom of the trenches and avoiding undesired damage ... | 10/25/2005 |
| 6943088 | Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner roun... | 09/13/2005 |
| 6921705 | Method for forming isolation layer of semiconductor device A method for forming an isolation layer of a semiconductor device. The method includes: a) sequentially laminating a pad oxide layer and pad nitride layer on a semiconductor substrate; b) selectively removing the pad nitride layer, selectively removing the pad oxide... | 07/26/2005 |
| 6905953 | Selective passivation of exposed silicon A method for applying a passivation layer selectively on an exposed silicon surface from a liquid phase solution supersaturated in silicon dioxide. The immersion is conducted at substantially atmospheric temperature and pressure and achieves an effective passivation... | 06/14/2005 |
| 6794259 | Method for fabricating self-aligning mask layers A method for fabricating a self-aligning mask layer includes the steps of forming a surface to be masked in a carrier substrate, the surface having different radii of curvature, forming an undensified conformal insulation layer on the surface such that, on account o... | 09/21/2004 |
| 6787426 | Method for forming word line of semiconductor device A method for forming word line of semiconductor device wherein a lower portion of the word line on the channel region is a I-type and a upper portion of the word line is a line-type is disclosed. The method comprises (a) forming a sacrificial insulation film on a se... | 09/07/2004 |
