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| Number | Title | Issue Date |
| 8133798 | Method for producing ink-jet head There is provided a method for producing an ink jet head. The method includes: first oxidizing in which, in an SOI substrate having a first SiO2 layer between a first Si layer and a second Si layer, among the first Si layer and the second Si layer, at lea... | 03/13/2012 |
| 8129254 | Semiconductor device and manufacturing method thereof A method of manufacturing a semiconductor device, includes forming an insulating film of a material having a low relative dielectric constant on a substrate, forming an SiOCH film on the insulating film in a chamber, forming an SiO2 film continuously on t... | 03/06/2012 |
| 7709349 | Semiconductor device manufactured using a gate silicidation involving a disposable chemical/mechanical polishing stop layer In one aspect, there is provided a method of manufacturing a semiconductor device that comprises placing a blocking layer, a CMP stop layer and a bulk oxide layer over an oxide cap layer that is located over gate structures and source/drains located adjacent thereto... | 05/04/2010 |
| 7588996 | Oxide pattern forming method and patterning method of semiconductor device An oxide pattern forming method comprises forming an oxide layer on a semiconductor substrate, implanting boron ions of not less than 1.0×1016 atoms/cm2 onto the oxide layer in a given region, and wet-etching the oxide layer in the remaining r... | 09/15/2009 |
| 7371659 | Substrate laser marking A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewal... | 05/13/2008 |
| 7320927 | In situ hardmask pullback using an in situ plasma resist trim process The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over t... | 01/22/2008 |
| 7312132 | Field insulator FET device and fabrication method thereof A FinFET and a fabrication method thereof. The FinFET device includes an SOI substrate realized through a substrate, a buried oxide layer formed on the substrate, and a silicon epitaxial layer formed on predetermined areas of the buried oxide layer. A gate oxide lay... | 12/25/2007 |
| 7309641 | Method for rounding bottom corners of trench and shallow trench isolation process A method for rounding the bottom corners of a trench is described. In the method, an etching process is performed using a fluorocarbon compound with at least two carbon atoms, He and O2 as an etching gas to round the bottom corners of the trench. ... | 12/18/2007 |
| 7294536 | Process for manufacturing an SOI wafer by annealing and oxidation of buried channels A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.... | 11/13/2007 |
| 7279426 | Like integrated circuit devices with different depth The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, ... | 10/09/2007 |
| 7271467 | Multiple oxide thicknesses for merged memory and logic applications Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologi... | 09/18/2007 |
| 7268082 | Highly selective nitride etching employing surface mediated uniform reactive layer films Disclosed is a method of selectively etching nitride in a chemical downstream etching process. The invention begins by placing a wafer having oxide regions and nitride regions in a chamber. Then, the invention performs a chemical downstream etching process using CH | 09/11/2007 |
| 7265014 | Avoiding field oxide gouging in shallow trench isolation (STI) regions A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI regi... | 09/04/2007 |
| 7259053 | Methods for forming a device isolation structure in a semiconductor device Methods of forming a device isolation structure in a semiconductor device are disclosed. A disclosed method comprises forming a p-type well and an n-type well in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate electrode material... | 08/21/2007 |
| 7256135 | Etching method and computer storage medium storing program for controlling same An etching method of the present invention includes a first and a second process. In the first process, pattern widths of a pre-patterned mask layer are increased by depositing plasma reaction products on sidewalls of the mask layer. In the second process, a layer t... | 08/14/2007 |
| 7256100 | Manufacturing method of semiconductor device having trench type element isolation A semiconductor substrate including a first region, a second region larger than the first region and an isolation region is provided. A mask layer is selectively formed on the first and second regions. A trench is formed on the isolation region. A first isolation ma... | 08/14/2007 |
| 7214586 | Methods of fabricating nonvolatile memory device A method of fabricating nonvolatile memory devices. The method includes forming a tunnel oxide layer, a stacked oxide layer, a polysilicon layer for a control gate, a buffer oxide layer and a buffer nitride layer in order on the entire surface of a semiconductor sub... | 05/08/2007 |
| 7211523 | Method for forming field oxide A method for forming a field oxide is disclosed. In one embodiment, the method comprises providing a semiconductor structure having a substrate, a pad oxide, and a patterned barrier layer, performing a dry oxidation process to form a first field oxide on the substra... | 05/01/2007 |
| 7189628 | Fabrication of trenches with multiple depths on the same substrate Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches an... | 03/13/2007 |
| 7141862 | Semiconductor device and method for manufacturing the same A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage tran... | 11/28/2006 |
| 7141850 | Gated semiconductor assemblies and methods of forming gated semiconductor assemblies In one aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a silicon nitride layer over and against a floating gate; and b) forming a control gate over the silicon nitride layer. In another aspect, the invention ... | 11/28/2006 |
| 7109120 | Profiled standoff structure and method for optical display package A method for forming a standoff structure for devices, e.g., optical devices, integrated circuit devices, micro-electrical mechanical systems (i.e., MEMS). The method includes providing a substrate (e.g., silicon wafer), which has a first surface region characterize... | 09/19/2006 |
| 7101814 | Masking without photolithography during the formation of a semiconductor device A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions, such as a memory transistor array, and widely-spaced regions, such as a periphery. Under conditions specifie... | 09/05/2006 |
| 7057263 | Semiconductor wafer assemblies comprising photoresist over silicon nitride materials In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) form... | 06/06/2006 |
| 7052969 | Method for semiconductor wafer planarization by isolation material growth A method of manufacturing a planarized semiconductor wafer in which a semiconductor wafer is provided with a chemical-mechanical polishing stop layer deposited thereon. A photoresist layer is processed and used to form a patterned chemical-mechanical polishing stop ... | 05/30/2006 |
| 7053007 | Method for fabricating semiconductor integrated circuit device A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vic... | 05/30/2006 |
| 7045435 | Shallow trench isolation method for a semiconductor wafer The present invention relates to a shallow trench isolation method of a semiconductor wafer which fills dielectric material into shallow trenches between components on the surface of the semiconductor wafer to electrically isolate the components. This method can pre... | 05/16/2006 |
| 7045880 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility of approxim... | 05/16/2006 |
| 7037768 | Methods of etching intermediate silicon germanium layers using ion implantation to promote selectivity An integrated circuit device structure can be formed by forming an implant mask having a window therein on a structure including upper and lower Si layers and an intermediate SiGex layer therebetween. Ions are implanted through the upper Si layer and into... | 05/02/2006 |
| 7023751 | Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage The required refresh rate of a DRAM is reduced by biasing active digit lines to a slight positive voltage to reduce the sub threshold current leakage of access transistors in memory cells that are not being accessed. The slight positive voltage is provided by a volt... | 04/04/2006 |
| 7015115 | Method for forming deep trench isolation and related structure According to one embodiment, a structure comprises a substrate and a field oxide region, where the field oxide region has a top surface, and where the top surface of the field oxide region comprises substantially no cavities caused by lateral etching. The structure ... | 03/21/2006 |
| 7012005 | Self-aligned differential oxidation in trenches by ion implantation In accordance with the present invention, a trench MOSFET is formed by creating a trench in a semiconductor substrate. A portion of either a side wall of the trench or the bottom of the trench is implanted with an implant species. An insulating layer is then grown o... | 03/14/2006 |
| 6991994 | Method of forming rounded corner in trench A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxid... | 01/31/2006 |
| 6960818 | Recessed shallow trench isolation structure nitride liner and method for making same A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling a trench with a photoresist plug and removing a portion of the photor... | 11/01/2005 |
| 6960821 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility of approxim... | 11/01/2005 |
| 6949448 | Local oxidation of silicon (LOCOS) method employing graded oxidation mask A method for forming a local oxidation of silicon (LOCOS) isolation region on a silicon substrate. A series of patterned graded oxidation mask layers formed of a material comprising silicon, oxygen and nitrogen is formed. The series of patterned graded oxidation mas... | 09/27/2005 |
| 6943088 | Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner roun... | 09/13/2005 |
| 6943072 | Adjustable threshold isolation transistor An method and apparatus for high voltage control of isolation region transistors (320) in an integrated circuit. Isolation region transistors (320) are formed between active devices by selective implantation of channel stop implants (140). Isola... | 09/13/2005 |
| 6927169 | Method and apparatus to improve thickness uniformity of surfaces for integrated device manufacturing A method and apparatus for the formation of oxide in a manner having a planarizing effect on underlying material, e.g., silicon. In particular, an oxide having a nonuniform thickness profile is grown on the underlying material. The nonuniform thickness profile of th... | 08/09/2005 |
| 6927138 | Method of semiconductor device fabrication Provided is a method of semiconductor device fabrication capable of rounding the sharp edge portions of trenches so as to form device isolation regions having high electrical reliability. A semiconductor substrate comprising a lattice-strain relaxed silicon germaniu... | 08/09/2005 |
