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| Number | Title | Issue Date |
| 8143139 | Method of fabricating extended drain MOS transistor A method of fabricating an extended drain MOS transistor which reduces a design rule and prevents the generation of leakage current. The method includes sequentially forming a diffusion film, a first conductive epitaxial layer, a gate oxide layer and a hard mask lay... | 03/27/2012 |
| 8067293 | Power semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same. The method includes preparing a semiconductor substrate having high-voltage and low-voltage device regions, forming a field insulating layer in the high-voltage device region, forming a first gate oxide ... | 11/29/2011 |
| 7994020 | Method of forming finned semiconductor devices with trench isolation A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor mater... | 08/09/2011 |
| 7964474 | Use of field oxidation to simplify chamber fabrication in microfluidic devices A method includes growing a first oxide region concurrently with a second oxide region in a substrate and forming an inlet path to the first oxide region, the inlet path exposing a first surface of the first oxide region. The method also includes removing the first ... | 06/21/2011 |
| 7816231 | Device structures including backside contacts, and methods for forming same The present invention relates to device structures having backside contacts that extend from a back surface of a substrate through the substrate to electrically contact frontside semiconductor devices. The substrate preferably further includes one or more alignment ... | 10/19/2010 |
| 7416947 | Method of fabricating trench MIS device with thick oxide layer in bottom of trench A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectr... | 08/26/2008 |
| 7393770 | Backside method for fabricating semiconductor components with conductive interconnects A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of ... | 07/01/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7358588 | Trench isolation type semiconductor device which prevents a recess from being formed in a field region A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active ... | 04/15/2008 |
| 7358596 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 04/15/2008 |
| 7354818 | Process for high voltage superjunction termination A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termin... | 04/08/2008 |
| 7348254 | Method of fabricating fin field-effect transistors A method of fabricating a fin field-effect transistor that may enable a reduction in the number of process steps, by forming the fin structure by etching away a predetermined thickness of an element isolation layer. The method includes steps of sequentially forming ... | 03/25/2008 |
| 7324736 | Intelligent recording control system A method and system for synchronizing recording of data transferred from a video source device to a recording device is disclosed. The method and system include analyzing an input signal from the source device based on a set of rules. In response to detecting a sour... | 01/29/2008 |
| 7321141 | Image sensor device and manufacturing method thereof A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. T... | 01/22/2008 |
| 7300834 | Methods of forming wells in semiconductor devices Disclosed herein are methods of forming a well in a semiconductor device, in which a well end point under a trench is formed deeper than other area by well implantation prior to trench filling and by which leakage current is minimized. In one example, the disclosed ... | 11/27/2007 |
| 7297599 | Method of fabricating semiconductor device A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a sur... | 11/20/2007 |
| 7265022 | Method of fabricating semiconductor device with STI structure A method of fabricating a semiconductor device, includes depositing, on a semiconductor substrate, a gate insulating film, a polycrystalline or amorphous silicon film, a silicon nitride film and a silicon oxide film sequentially, patterning a resist for forming a pl... | 09/04/2007 |
| 7256100 | Manufacturing method of semiconductor device having trench type element isolation A semiconductor substrate including a first region, a second region larger than the first region and an isolation region is provided. A mask layer is selectively formed on the first and second regions. A trench is formed on the isolation region. A first isolation ma... | 08/14/2007 |
| 7218438 | Optical electronic device with partial reflector layer An optical electronic device with a partial reflector layer is disclosed. The device includes a first reflector and a second reflector that define an optical cavity therebetween. The second reflector includes at least one material having a refractive index and an ex... | 05/15/2007 |
| 7189592 | Manufacturable single-chip hydrogen sensor A robust single-chip hydrogen sensor and a method for fabricating such a sensor. By utilizing an interconnect metallization material that is the same or similar to the material used to sense hydrogen, or that is capable of withstanding an etchant used to pattern a h... | 03/13/2007 |
| 7183173 | Method for forming isolation film in semiconductor device A method for forming an isolation film of a semiconductor device is disclosed which includes forming trenches in a semiconductor substrate, forming a first HDP oxide film in the formed trenches, performing an etch-back process using a mixing gas of C2F | 02/27/2007 |
| 7153731 | Method of forming a field effect transistor with halo implant regions A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed withi... | 12/26/2006 |
| 7141483 | Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill A method of filling a gap defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate and providing a flow of an oxidizing gas to the chamber. The method also includes deposit... | 11/28/2006 |
| 7141485 | Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits A method for reducing sidewall capacitance by 25% or more in an STI structure is described. A conformal barrier layer is deposited on sloped sidewalls in a shallow trench within a substrate. The trench is filled with a low k dielectric material which is planarized a... | 11/28/2006 |
| 7135417 | Method of forming a semiconductor device In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of oxidation steps, with optional interposed cleanings, as well as an optional conditioning step after oxida... | 11/14/2006 |
| 7118966 | Methods of forming conductive lines This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first... | 10/10/2006 |
| 7087489 | Method of fabricating trap type nonvolatile memory device A method of forming a trap type nonvolatile memory device is disclosed. The method includes forming a cell gate insulating layer on a semiconductor substrate. The semiconductor substrate includes a peripheral circuit region and a cell array region. A sacrificial pat... | 08/08/2006 |
| 7081398 | Methods of forming a conductive line A method of forming a local interconnect includes forming an isolation trench within a semiconductor substrate. A first trench isolation material is deposited to within the trench. First isolation material is removed effective to form a line trench into a desired lo... | 07/25/2006 |
| 7078312 | Method for controlling etch process repeatability Plasma etch processes incorporating etch chemistries which include hydrogen. In particular, high density plasma chemical vapor deposition-etch-deposition processes incorporating etch chemistries which include hydrogen that can effectively fill high aspect ratio (typ... | 07/18/2006 |
| 7071043 | Methods of forming a field effect transistor having source/drain material over insulative material In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within t... | 07/04/2006 |
| 7071076 | Method of manufacturing semiconductor device A semiconductor device has an STI oxide film (106), of which surface is positioned higher than the surface of the silicon substrate (100) to prevent a pointed portion and a thin film thickness of a gate oxide film (108). The gate oxide film (... | 07/04/2006 |
| 7068870 | Variable width waveguide for mode-matching and method for making A variable width waveguide useful for mode matching between dissimilar optical waveguides and optical fibers and a method for making the same is described. In one embodiment, a tapered waveguide is etched in a substrate, a cladding material is laid over the upper su... | 06/27/2006 |
| 7064045 | Laser based method and device for forming spacer structures for packaging optical reflection devices A method for forming a patterned silicon bearing material, e.g., silicon substrate. The method includes providing a silicon substrate, which has a surface region and a backside region. The method includes forming a plurality of recessed regions on the surface region... | 06/20/2006 |
| 7049206 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 05/23/2006 |
| 7045435 | Shallow trench isolation method for a semiconductor wafer The present invention relates to a shallow trench isolation method of a semiconductor wafer which fills dielectric material into shallow trenches between components on the surface of the semiconductor wafer to electrically isolate the components. This method can pre... | 05/16/2006 |
| 7013562 | Method of using micro-contact imprinted features for formation of electrical interconnects for substrates An imprinting stamp to imprint an opening in a material layer in which the imprint stamp has a coating of a seed material. The seed material is transferred onto the surface within the opening to operate as a seed for filling the opening. In one embodiment, low surfa... | 03/21/2006 |
| 6997985 | Semiconductor, semiconductor device, and method for fabricating the same Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the s... | 02/14/2006 |
| 6967141 | Method of manufacturing a semiconductor integrated circuit device having a trench A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall ... | 11/22/2005 |
| 6963510 | Programmable capacitor and method of operating same A programmable capacitor in an integrated circuit (IC) comprises a conductive line located parallel to an interconnect. When a bias voltage is applied to the conductive line, a parasitic capacitance is created between the interconnect and the conductive line. By pro... | 11/08/2005 |
| 6960510 | Method of making sub-lithographic features A method of forming a structure having sub-lithographic dimensions is provided. The method includes: forming a chamfered mandrel on a substrate, the mandrel having an angled surface; and performing an angled ion implantation to obtain an implanted shadow region in t... | 11/01/2005 |
