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| Number | Title | Issue Date |
| 8173517 | Method for forming a self-aligned isolation structure utilizing sidewall spacers as an etch mask and remaining as a portion of the isolation structure The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be... | 05/08/2012 |
| 8153502 | Methods for filling trenches in a semiconductor material Methods of filling cavities or trenches. More specifically, methods of filling a cavity or trench in a semiconductor layer are provided. The methods include depositing a first dielectric layer into the trench by employing a conformal deposition process. Next, the fi... | 04/10/2012 |
| 8062955 | Substrate processing method and substrate processing apparatus A CoWB film is formed as a cap metal on a Cu interconnection line formed on a substrate or wafer W, by repeating a plating step and a post-cleaning step a plurality of times. The plating step is arranged to apply electroless plating containing CoWB onto the Cu inter... | 11/22/2011 |
| 8017496 | Methods of manufacturing a semiconductor device In a method of manufacturing a semiconductor device, a mask pattern is formed on an active region of a substrate. An exposed portion of the substrate is removed to form a trench in the substrate. A preliminary first insulation layer is formed on a bottom and sidewal... | 09/13/2011 |
| 7994019 | Silicon-ozone CVD with reduced pattern loading using incubation period deposition Aspects of the disclosure pertain to methods of depositing conformal silicon oxide layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively un... | 08/09/2011 |
| 7906407 | Shallow trench isolation structures and a method for forming shallow trench isolation structures A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present... | 03/15/2011 |
| 7883987 | Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a f... | 02/08/2011 |
| 7807546 | SRAM cell having stepped boundary regions and methods of fabrication A semiconductor device comprises a substrate. In addition, the semiconductor device comprises an active region and an isolation region. The active region is in the substrate and comprises a semiconductor material. The isolation region is also in the substrate, adjac... | 10/05/2010 |
| 7795110 | Trench isolation type semiconductor device which prevents a recess from being formed in a field region and method of fabricating the same A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active ... | 09/14/2010 |
| 7749860 | Method for forming a self-aligned T-shaped isolation trench The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof which cause current and charge leakage to an adjacent active area. The... | 07/06/2010 |
| 7745305 | Method of removing an oxide and method of filling a trench using the same A method of removing a portion of an oxide layer includes forming first byproducts by reacting a reaction gas with the oxide layer, the reaction gas including fluorine and nitrogen, reacting the reaction gas with the first byproducts to form second byproducts, and r... | 06/29/2010 |
| 7678666 | Crystallization method of amorphous silicon for forming large grain with single pulse laser A layer structure comprising substrate, a metal layer, a first amorphous silicon layer, an insulating layer, and a second amorphous silicon layer, and a method of crystallizing the second amorphous silicon layer by irradiating single pulse laser to the layer structu... | 03/16/2010 |
| 7651923 | Method for forming transistor of semiconductor device A method for forming a transistor of a semiconductor device, includes forming a trench by etching a semiconductor substrate on which a pad oxide film and a pad nitride film are sequentially formed; forming a isolation oxide film by filling the trench with oxide; rem... | 01/26/2010 |
| 7608519 | Method of fabricating trench isolation of semiconductor device In a method of fabricating a trench isolation structure of a semiconductor device, excellent gap filling properties are attained, without the generation of defects. In one aspect, the method comprises: loading a substrate with a trench formed therein into a high-den... | 10/27/2009 |
| 7534698 | Methods of forming semiconductor devices having multilayer isolation structures A semiconductor device includes a first structure having a recess having a bottom and opposing side surfaces, and a second structure conformally disposed on the bottom and side surfaces of the recess. The second structure includes a multilayer having two layers havi... | 05/19/2009 |
| 7498233 | Method of forming an insulation layer structure having a concave surface and method of manufacturing a memory device using the same A method of forming an isolation layer structure for a semiconductor device includes forming a first structure on a substrate, the first structure including an insulation layer pattern having a sacrificial pattern therein, the sacrificial pattern having an etching r... | 03/03/2009 |
| 7494895 | Method of fabricating a three-dimensional MOSFET employing a hard mask spacer A method of fabricating a 3D field effect transistor employing a hard mask spacer includes forming a hard mask pattern on a semiconductor substrate. The semiconductor substrate is etched using the hard mask pattern as an etch mask to form a trench that defines an ac... | 02/24/2009 |
| 7482246 | Trench isolation structure in a semiconductor device and method for fabricating the same A trench isolation structure in a semiconductor device is provided. A semiconductor substrate has cell regions and peripheral circuit regions. First trenches have a predetermined depth and are formed in the semiconductor substrate at the cell regions. A first sidewa... | 01/27/2009 |
| 7482247 | Conformal nanolaminate dielectric deposition and etch bag gap fill process Conformal nanolaminate dielectric deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of void... | 01/27/2009 |
| 7442618 | Method to engineer etch profiles in Si substrate for advanced semiconductor devices Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill t... | 10/28/2008 |
| 7416955 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-cont... | 08/26/2008 |
| 7387943 | Method for forming layer for trench isolation structure A method for forming a thermal oxide layer on the surface of a semiconductor substrate exposed during a semiconductor fabricating process. The thermal oxide layer is to be thin to minimize silicon substrate defects caused by volume expansion. A chemical vapor deposi... | 06/17/2008 |
| 7371647 | Methods of forming transistors The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nit... | 05/13/2008 |
| 7368366 | Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ... | 05/06/2008 |
| 7364981 | Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ... | 04/29/2008 |
| 7361572 | STI liner modification method A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further i... | 04/22/2008 |
| 7362784 | Laser irradiation method, laser irradiation apparatus, and semiconductor device An object of the present invention is obtaining a semiconductor film with uniform characteristics by improving irradiation variations of the semiconductor film. The irradiation variations are generated due to scanning while irradiating with a linear laser beam of th... | 04/22/2008 |
| 7358150 | Trench isolation structure for a semiconductor device with reduced sidewall stress and a method of manufacturing the same By forming a non-oxidizable liner in isolation trenches, the creation of compressive stress may be significantly reduced, wherein, in illustrative embodiments, silicon nitride may be used as liner material. For this purpose, the etch behavior of the silicon nitride ... | 04/15/2008 |
| 7358190 | Methods of filling gaps by deposition on materials having different deposition rates Methods of forming material in a gap in a substrate include forming a pattern to define a gap on a substrate. A bottom oxide layer is formed on a surface of the substrate and substantially filling the gap. The bottom oxide layer is etched back inside an opening in t... | 04/15/2008 |
| 7358558 | Flash memory device A floating gate of a flash memory device is formed in a moat formed in an isolation film. Therefore, an electric field applied between a control gate and a channel region upon cycling can be precluded or mitigated. A distance between the control gate and the channel... | 04/15/2008 |
| 7358145 | Method of fabricating shallow trench isolation structure A method of fabricating a shallow trench isolation structure is provided. A substrate is provided with a pad layer, a mask layer and a shallow trench formed therein. A liner oxide layer is formed on the sidewall of the shallow trench and then a silicon nitride layer... | 04/15/2008 |
| 7358191 | Method for decreasing sheet resistivity variations of an interconnect metal layer According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenche... | 04/15/2008 |
| 7351661 | Semiconductor device having trench isolation layer and a method of forming the same A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer fo... | 04/01/2008 |
| 7339224 | Trench capacitor and corresponding method of production The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first region (1a), provided in the substrate (1), as first capacitor electro... | 03/04/2008 |
| 7338850 | Method for manufacturing device isolation film of semiconductor device A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to pr... | 03/04/2008 |
| 7335564 | Method for forming device isolation layer of semiconductor device A method for forming a device isolation device of a semiconductor device is disclosed. The method includes the steps of forming a moat pattern for forming a trench on a semiconductor substrate, forming a trench by etching the semiconductor substrate to a predetermin... | 02/26/2008 |
| 7332409 | Methods of forming trench isolation layers using high density plasma chemical vapor deposition A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed. ... | 02/19/2008 |
| 7320926 | Shallow trench filled with two or more dielectrics for isolation and coupling for stress control A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and fi... | 01/22/2008 |
| 7319062 | Trench isolation method with an epitaxially grown capping layer A trench isolation method for a semiconductor device, wherein a capping layer formed of an insulating material fills a recess generated at a border edge between an active area and an inactive area. The border edge is defined by a trench filled with insulating materi... | 01/15/2008 |
| 7314809 | Method for forming a shallow trench isolation structure with reduced stress A method for forming a shallow trench isolation (STI) structure with reduced stress is described. An amorphous silicon layer is deposited on a trench surface of a shallow trench isolation structure, and the amorphous silicon is then oxidized by thermal oxidation to ... | 01/01/2008 |
