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| Number | Title | Issue Date |
| 7915139 | CVD flowable gap fill The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Rea... | 03/29/2011 |
| 7888233 | Flowable film dielectric gap fill process Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manne... | 02/15/2011 |
| 7736992 | Isolation trench geometry for image sensors A pixel cell including a substrate having a top surface. A photo-conversion device is at a surface of the substrate and a trench is in the substrate adjacent the photo-conversion device. The trench has sidewalls and a bottom. At least one sidewall is angled less tha... | 06/15/2010 |
| 7678665 | Deep STI trench and SOI undercut enabling STI oxide stressor A method for imparting stress to the channel region of a transistor is provided. In accordance with the method, a semiconductor layer (307) is provided which has a dielectric layer (305) disposed beneath it. A trench (319) is created which exten... | 03/16/2010 |
| 7524735 | Flowable film dielectric gap fill process Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manne... | 04/28/2009 |
| 7442621 | Semiconductor process for forming stress absorbent shallow trench isolation structures A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping... | 10/28/2008 |
| 7375004 | Method of making an isolation trench and resulting isolation trench A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of t... | 05/20/2008 |
| 7358191 | Method for decreasing sheet resistivity variations of an interconnect metal layer According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenche... | 04/15/2008 |
| 7358104 | Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first ... | 04/15/2008 |
| 7354818 | Process for high voltage superjunction termination A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termin... | 04/08/2008 |
| 7332409 | Methods of forming trench isolation layers using high density plasma chemical vapor deposition A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed. ... | 02/19/2008 |
| 7282412 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/16/2007 |
| 7279429 | Method to improve ignition in plasma etching or plasma deposition steps In one embodiment, the present invention relates to a method for increasing the ignition reliability of a plasma in a plasma reactor, the method comprising: supplying a source gas to the plasma reactor, the source gas comprising: (a) at least one reactive compound; ... | 10/09/2007 |
| 7276411 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/02/2007 |
| 7238568 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 07/03/2007 |
| 7235459 | Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ... | 06/26/2007 |
| 7223701 | In-situ sequential high density plasma deposition and etch processing for gap fill During microelectronic processing of a substrate, a gap on the substrate surface may be filled with a material by alternating deposition and etch processes while the substrate remains in the same process chamber. Alternating deposition and etch processes allows the ... | 05/29/2007 |
| 7214580 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, f... | 05/08/2007 |
| 7211499 | Methods of forming silicon dioxide layers, and methods of forming trench isolation regions A method of forming a silicon dioxide layer includes forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a depos... | 05/01/2007 |
| 7199021 | Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner... | 04/03/2007 |
| 7193277 | Application of different isolation schemes for logic and embedded memory The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relat... | 03/20/2007 |
| 7193269 | MOS semiconductor device While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor... | 03/20/2007 |
| 7179691 | Method for four direction low capacitance ESD protection The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Vss protection device. In add... | 02/20/2007 |
| 7170126 | Structure of vertical strained silicon devices A trench capacitor vertical-transistor DRAM cell in a SiGe wafer compensates for overhang of the pad nitride by forming an epitaxial strained silicon layer on the trench walls that improves transistor mobility, removes voids from the poly trench fill and reduces res... | 01/30/2007 |
| 7169697 | Semiconductor device and manufacturing method of the same Disclosed is a semiconductor device, comprising a first wiring structure formed on a semiconductor substrate and including a first plug and a first wiring formed on the first plug, and a second wiring structure formed on the semiconductor substrate belonging to the ... | 01/30/2007 |
| 7163869 | Shallow trench isolation structure with converted liner layer A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised o... | 01/16/2007 |
| 7157385 | Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silico... | 01/02/2007 |
| 7157351 | Ozone vapor clean method A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide... | 01/02/2007 |
| 7153728 | Estimation of remaining film thickness distribution, correction of patterning and insulation film removing masks with remaining film thickness distribution, and production of semiconductor device with corrected patterning and insulation film removing masks By making use of the remaining film thickness distribution (CMP pattern ratio) that is a distribution of estimates of the remaining film thickness after the CMP process, the first region A is abstracted from the patterning mask that corresponds to the region X where... | 12/26/2006 |
| 7129148 | Methods for manufacturing semiconductor devices and semiconductor devices having trench isolation regions A semiconductor device having trench isolation regions in which leaks are suppressed may be formed using the following steps. (a) Forming a trench 32 in a semiconductor layer 12; (b) forming a dielectric layer 40 that fills the trench 32;... | 10/31/2006 |
| 7125815 | Methods of forming a phosphorous doped silicon dioxide comprising layer This invention includes methods of forming phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide comprisin... | 10/24/2006 |
| 7119404 | High performance strained channel MOSFETs by coupled stress effects Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strain... | 10/10/2006 |
| 7118987 | Method of achieving improved STI gap fill with reduced stress A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; ... | 10/10/2006 |
| 7112513 | Sub-micron space liner and densification process A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon,... | 09/26/2006 |
| 7109094 | Method for preventing leakage in shallow trench isolation Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A secon... | 09/19/2006 |
| 7102184 | Image device and photodiode structure The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first conductivity type with a first impurity concentration form a region surrounding at least part of the isolation re... | 09/05/2006 |
| 7078313 | Method for fabricating an integrated semiconductor circuit to prevent formation of voids Recesses between gate layer stacks are filled with a first electrically insulating material. Cavities or voids are opened up during the removal of a portion of the first insulating material. These voids are filled during the application of a conductive layer and can... | 07/18/2006 |
| 7074691 | Method of manufacturing a semiconductor integrated circuit device that includes forming dummy patterns in an isolation region prior to filling with insulating material A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a... | 07/11/2006 |
| 7074690 | Selective gap-fill process Methods for selectively depositing a solid material on a substrate having gaps of dimension on the order of about 100 nm or less are disclosed. The methods involve exposing the substrate to a precursor of a solid material, such that the precursor forms liquid region... | 07/11/2006 |
| 7071076 | Method of manufacturing semiconductor device A semiconductor device has an STI oxide film (106), of which surface is positioned higher than the surface of the silicon substrate (100) to prevent a pointed portion and a thin film thickness of a gate oxide film (108). The gate oxide film (... | 07/04/2006 |
