Class 438/435 - Multiple insulative layers in groove

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making electrically isolated laterally spaced
No. of patents: 700
Last issue date: 05/08/2012

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Number	Title	Issue Date
8173515	Method for manufacturing semiconductor device An oxide film and a liner film are formed on an inner wall of a trench in a semiconductor substrate. After filling an SOD film in the trench, a heat treatment is carried out. Part of the liner film in contact with the SOD film is removed to expose part of the SOD fi...	05/08/2012
8173516	Method of forming shallow trench isolation structure An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed extending from the top surface into the substrate. The trench has sidewalls and a bot...	05/08/2012
8163627	Method of forming isolation layer of semiconductor device A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is fo...	04/24/2012
8158488	Method of increasing deposition rate of silicon dioxide on a catalyst Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to ...	04/17/2012
8143138	Method for fabricating interconnect structures for semiconductor devices Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a dual-damascene method having trenches then vias formed. The method includes novel liner depositions after the tr...	03/27/2012
8058141	Recessed gate electrode MOS transistor and method for fabricating the same Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exp...	11/15/2011
8030173	Silicon nitride hardstop encapsulation layer for STI region A semiconductor process and apparatus provides an encapsulated shallow trench isolation region by forming a silicon nitride layer (96) to cover a shallow trench isolation region (95), depositing a protective dielectric layer (97, 98) over the si...	10/04/2011
8030172	Isolation technology for submicron semiconductor devices A semiconductor structure has a substrate having a trench, an isolation dielectric in the trench, and a stress buffer layer, between the substrate and the dielectric. Semiconductor devices containing the semiconductor structure may have higher reliability, and may h...	10/04/2011
8003490	Integrated circuit and method including an isolation arrangement An integrated circuit and method including an isolation arrangement. One embodiment provides a substrate having trenches and mesa regions and also auxiliary structures on the mesa regions. A first isolation structure covers side walls and a bottom region of the tren...	08/23/2011
8003489	Method for forming isolation layer in semiconductor device A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate. A flowable insulation layer is formed to fill the trench. The flowable insulation layer is recessed. A buried insulation layer is deposited on t...	08/23/2011
7998831	Planarized passivation layer for semiconductor devices A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer f...	08/16/2011
7998832	Semiconductor device with isolation trench liner, and related fabrication methods A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor ma...	08/16/2011
7989310	Filling of insulation trenches using CMOS standard processes for creating dielectrically insulated areas on a SOI disk Insulating trenches isolate regions of a semiconductor layer and include hermetically sealed voids. After forming a trench, a first fill of SiO2 is formed by a CVD process with the oxide layers having increasing thickness toward the upper trench edges for...	08/02/2011
7968425	Isolation regions Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process,...	06/28/2011
7951686	Method of manufacturing semiconductor device having device characteristics improved by straining surface of active region A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trenc...	05/31/2011
7939422	Methods of thin film process A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space...	05/10/2011
7927968	Dual stress STI The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transisto...	04/19/2011
7919390	Isolation structure in memory device and method for fabricating the isolation structure An isolation structure in a memory device and a method for fabricating the isolation structure. In the method, a first trench is formed in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. A liner l...	04/05/2011
7915138	Methods of manufacturing non-volatile memory devices In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the s...	03/29/2011
7902037	Isolation structure in memory device and method for fabricating the same A method for fabricating an isolation structure in a memory device includes forming a first trench in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. The method also includes oxidating the surface...	03/08/2011
7892944	Method of forming transistor in semiconductor device A method of forming a transistor in a semiconductor device includes forming device isolation structures in a substrate to define an active region. An oxide-based layer and a nitride-based layer are then formed between the active region and the device isolation struc...	02/22/2011
7892942	Methods of forming semiconductor constructions, and methods of forming isolation regions Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a tempe...	02/22/2011
7892943	Isolation trenches for memory devices A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first di...	02/22/2011
7871897	Method of forming shallow trench isolation regions in devices with NMOS and PMOS regions A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the...	01/18/2011
7858492	Method of filling a trench and method of forming an isolating layer structure using the same A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface...	12/28/2010
7785985	Methods of manufacturing semiconductor devices Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the charact...	08/31/2010
7785984	Manufacturing method for semiconductor device A manufacturing method for a semiconductor device includes generating on a substrate liquid-phase silanol having fluidity by causing a source gas made of a material containing silicon to react with a source gas made of a material containing oxygen, introducing the s...	08/31/2010
7776713	Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant...	08/17/2010
7659181	Sub-micron space liner and filler process A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon,...	02/09/2010
7655534	Method of forming fin transistor A fin transistor is formed by forming a hard mask layer on a substrate having an active region and a field region. The hard mask layer is etched to expose the field region. A trench is formed by etching the exposed field region. The trench is filled with an SOG laye...	02/02/2010
7655535	Method for fabricating semiconductor device having trench isolation layer A method for fabricating a device isolation structure of a semiconductor device includes the steps of forming a pad oxide layer and a pad nitride layer over a semiconductor substrate including a cell region and a dummy region, etching a portion of the pad nitride la...	02/02/2010
7645679	Method for forming isolation layer in semiconductor devices A method for forming an isolation layer for a semiconductor device is provided. The preferred method is capable of securing a gap fill margin during formation of an isolation layer. A device isolation layer formed according to a preferred method includes a trench fo...	01/12/2010
7632737	Protection in integrated circuits A method including, prior to a plasma heat-up operation, forming a liner on structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between about ...	12/15/2009
7618876	Semiconductor device and method of manufacturing the same by filling a trench which includes an additional coating step A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transf...	11/17/2009
7611964	Method of forming isolation layer of semiconductor memory device The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge...	11/03/2009
7605049	Optical semiconductor device and manufacturing method for same A transistor that forms an integrated circuit, a photo detector and a micromirror are mounted on the same semiconductor substrate in an optical semiconductor device of the present invention, which has an antireflection film that is formed on the photo detector, a fi...	10/20/2009
7563690	Method for forming shallow trench isolation region A method for forming a shallow trench isolation (STI) structure is provided. A pad oxide layer and a nitride silicon layer are formed on a provided substrate sequentially. The pad oxide layer, the nitride silicon layer and the substrate are then etched to form a tre...	07/21/2009
7528052	Method for fabricating semiconductor device with trench isolation structure The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structur...	05/05/2009
7507635	CMOS image sensor and method of fabricating the same A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present invention includes a first-conductivity-type doping area formed in the dev...	03/24/2009
7494894	Protection in integrated circuits A method including, prior to a plasma heat-up operation, forming a liner on a structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between abou...	02/24/2009

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Class 438/435 - Multiple insulative layers in groove