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| Number | Title | Issue Date |
| 7790568 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes: providing a semiconductor substrate; forming a STI region on the semiconductor substrate; forming a channel region on the semiconductor substrate; implanting impurities into the STI region; and performing a t... | 09/07/2010 |
| 7727856 | Selective STI stress relaxation through ion implantation A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer havi... | 06/01/2010 |
| 7282412 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/16/2007 |
| 7276411 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/02/2007 |
| 7273794 | Shallow trench isolation fill by liquid phase deposition of SiO2 To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depo... | 09/25/2007 |
| 7271074 | Trench insulation in substrate disks comprising logic semiconductors and power semiconductors Disclosed is a layer arrangement (4b, 5b, 9b, 10, 9a, 5a, 4a) within an insulating trench, which insulates circuits with little distortion while being suitable for electrically insul... | 09/18/2007 |
| 7238568 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 07/03/2007 |
| 7214979 | Selectively deposited silicon oxide layers on a silicon substrate A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of... | 05/08/2007 |
| 7208390 | Semiconductor device structure and method for forming A semiconductor device structure has trenches of two widths or more. The smallest widths are to maximize density. The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories. These more demanding, wider i... | 04/24/2007 |
| 7192893 | Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relat... | 03/20/2007 |
| 7189629 | Method for isolating semiconductor devices A method of isolating semiconductor devices including forming a pad layer on a semiconductor substrate, forming a trench by etching the semiconductor substrate to a predetermined depth using the pad layer as an etch barrier, implanting ion impurities into a bottom o... | 03/13/2007 |
| 7109094 | Method for preventing leakage in shallow trench isolation Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A secon... | 09/19/2006 |
| 7078307 | Method for manufacturing single-sided buried strap in semiconductor devices A method for manufacturing a single-ended buried strap used in semiconductor devices is disclosed. According to the present invention, a trench capacitor structure is formed in a semiconductor substrate, wherein the trench capacitor structure has a contact surface l... | 07/18/2006 |
| 7078315 | Method for eliminating inverse narrow width effects in the fabrication of DRAM device The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The shallow trench surrounds an active area. A non-doped silicate glass (N... | 07/18/2006 |
| 7029753 | Multi-layer hard mask structure for etching deep trench in substrate A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first ... | 04/18/2006 |
| 6949446 | Method of shallow trench isolation formation and planarization Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of... | 09/27/2005 |
| 6939741 | IC chip manufacturing method It is an object of the invention to provide a method for manufacturing an IC chip wherein a wafer is prevented from being damaged and the ease of handling thereof is improved so that the wafer can be appropriately processed into IC chips, even if a thickness of the ... | 09/06/2005 |
| 6911374 | Fabrication method for shallow trench isolation region A fabrication method for a shallow trench isolation region is described. A part of the trench is filled with a first insulation layer, followed by performing a surface treatment process to form a surface treated layer on the surface of a part of the first insulation... | 06/28/2005 |
| 6787877 | Method for filling structural gaps and integrated circuitry A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a... | 09/07/2004 |
| 6773975 | Formation of a shallow trench isolation structure in integrated circuits In one embodiment, a transistor is fabricated by forming gate materials, such as a gate oxide layer and a gate polysilicon layer, prior to forming a shallow trench isolation (STI) structure. Forming the gate materials early in the process minimizes exposure of the S... | 08/10/2004 |
| 6750116 | Method for fabricating asymmetric inner structure in contacts or trenches The present invention provides a method for making an asymmetric inner structure in a contact or trench having a first sidewall, second sidewall, and a bottom in a semiconductor layer. A conformal dielectric layer is deposited on the interior surface of the contact ... | 06/15/2004 |
| 6551903 | Melt through contact formation method A thin film photovoltaic devices is described, having a glass substrate 11 over which is formed a thin film silicon device having an n++ layer 12, a p layer 13 and a dielectric layer 14 (typically silicon oxide or silicon nitride). To create a ... | 04/22/2003 |
| 6541350 | Method for fabricating shallow trench isolation A method for forming shallow trench isolation is disclosed. A pad oxide layer and a mask layer are sequentially formed on a substrate. Afterwards, an opening is formed through the mask layer and the pad oxide layer such that regions of the substrate are e... | 04/01/2003 |
| 6524499 | Transparent conductive film and display device The transparent conductive film of the present invention is formed to have a conductive layer containing at least ruthenium fine particles, gold fine particles and silver fine particles, the weight ratio of ruthenium fine particles and gold fine particles... | 02/25/2003 |
| 6475865 | Method of fabricating semiconductor device A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with... | 11/05/2002 |
| 6465304 | Method for fabricating a power semiconductor device having a floating island voltage sustaining layer A power semiconductor device and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by de... | 10/15/2002 |
| 6399468 | Semiconductor device and method of manufacturing the same To increase the withstand voltage and reduce ON-state resistance, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP layer (a P-type body region) formed so that the LP layer is adjac... | 06/04/2002 |
| 6388304 | Semiconductor device having buried-type element isolation structure and method of manufacturing the same The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side wall portion of the trench, to form a side wall. Further, io... | 05/14/2002 |
| 6376331 | Method for manufacturing a semiconductor device A semiconductor device is herein disclosed which comprises a plurality of element regions formed on a first conductive type semiconductor substrate, element isolation regions for isolating the element regions from each other, and gate electrodes on parts ... | 04/23/2002 |
| 6316330 | Method of fabricating a shallow trench isolation semiconductor device A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with... | 11/13/2001 |
| 6313009 | Fabrication method of semiconductor memory device with impurity regions surrounding recess A semiconductor device and a fabrication method thereof which are capable of achieving a lightly doped drain (LDD) construction and reducing a parasitic capacitance generated between an impurity area and a word line by forming a trench in a portion of a s... | 11/06/2001 |
| 6284626 | Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench With the present invention, a filled isolation trench is fabricated as part of an integrated circuit on a semiconductor wafer using nitrogen implantation into at least one side wall of the isolation trench. An isolation trench is etched within a layer of ... | 09/04/2001 |
| 6281068 | Method for buried plate formation in deep trench capacitors An improved method of forming the buried plate regions in deep trench capacitors used in DRAM memory semiconductor circuits in which the polymer used in the deep trench is etched down to the desired depth in a reactive ion etch tool using an O2... | 08/28/2001 |
| 6268297 | Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces A low-temperature pre-metal dielectric deposition process using phosphine-based chemistry in a high-density plasma chemical-vapor deposition technique. The process uses a phosphorous-doped oxide of up to 3.5 percent (wt) deposited at less than 350 degrees... | 07/31/2001 |
| 6265292 | Method of fabrication of a novel flash integrated circuit A method of fabricating a flash memory integrated circuit is described. In an embodiment of the present invention a dielectric filled trench isolation region is formed in a silicon substrate. The dielectric filled trench isolation region isolates a first ... | 07/24/2001 |
| 6248645 | Semiconductor device having buried-type element isolation structure and method of manufacturing the same The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side wall portion of the trench, to form a side wall. Further, io... | 06/19/2001 |
| 6225188 | Self aligned method for differential oxidation rate at shallow trench isolation edge A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably thro... | 05/01/2001 |
| 6214698 | Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer A method for filling a trench within a substrate. First a substrate is provided having a trench formed therein. The trench has a bottom surface and opposing side walls. An undoped silicon glass liner is then thermally grown to coat the bottom surface and ... | 04/10/2001 |
| 6121110 | Trench isolation method for semiconductor device A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor sub... | 09/19/2000 |
| 6114216 | Methods for shallow trench isolation The present invention provides systems, methods and apparatus for high temperature (at least about 500-800° C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed i... | 09/05/2000 |
