Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 8187950 | Method of eliminating micro-trenches during spacer etch A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a ... | 05/29/2012 |
| 8119496 | Semiconductor device and manufacturing method thereof A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a s... | 02/21/2012 |
| 8071462 | Isolation structures for integrated circuits and modular methods of forming the same A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be ... | 12/06/2011 |
| 8043934 | Methods of use and formation of a lateral bipolar transistor with counter-doped implant regions under collector and/or emitter regions A method for protecting a semiconductor circuit from electrostatic discharge is disclosed. An electrostatic discharge is received at a node. Current created by the electrostatic discharge is directed vertically into a semiconductor body, laterally through the semico... | 10/25/2011 |
| 8012849 | Semiconductor device and manufacturing method thereof A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediatel... | 09/06/2011 |
| 7994018 | Method for fabricating semiconductor device A method for fabricating a semiconductor device is disclosed. The method includes forming a first oxide film, a nitride film, and a second oxide film on a semiconductor substrate in succession, etching the second oxide film and the nitride film to form a second oxid... | 08/09/2011 |
| 7968424 | Method of implantation Provided is a method of implanting dopant ions to an integrated circuit. The method includes forming a first pixel and a second pixel in a substrate, forming an etch stop layer over the substrate, forming a hard mask layer over the etch stop layer, patterning the ha... | 06/28/2011 |
| 7858491 | Method of fabricating semiconductor device This invention relates to a method of fabricating a semiconductor device. A P well for a cell junction may be formed by performing an ion implantation process employing a zero tilt condition. Stress caused by collision between a dopant and a Si lattice within a semi... | 12/28/2010 |
| 7851328 | STI stress modulation with additional implantation and natural pad sin mask A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defi... | 12/14/2010 |
| 7776712 | Method of forming a semiconductor device There is provided a crystalline TFT in which reliability comparable to or superior to a MOS transistor can be obtained and excellent characteristics can be obtained in both an on state and an off state. A gate electrode of the crystalline TFT is formed of a laminate... | 08/17/2010 |
| 7759216 | Method for forming trench isolation A method for forming a trench isolation in a semiconductor device is provided. This is a novel method for rounding the top corners of trench isolations. The method ensures that rounded corner portions with a uniform shape are consistently formed regardless of the pa... | 07/20/2010 |
| 7741192 | Semiconductor device and manufacturing method thereof A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a s... | 06/22/2010 |
| 7670926 | Method for forming shallow trench isolation utilizing two filling oxide layers A method for forming shallow trench isolation in a semiconductor device. The method includes forming a trench in a predetermined depth on a semiconductor substrate, filling the trench with a first filing oxide, injecting an impurity into a portion of the first filli... | 03/02/2010 |
| 7443007 | Trench isolation structure having an implanted buffer layer The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a ... | 10/28/2008 |
| 7432148 | Shallow trench isolation by atomic-level silicon reconstruction Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to improve the silicon (Si) surface at the atomic level. Each of the exemplary methods creates a smooth STI sidew... | 10/07/2008 |
| 7429519 | Method of forming isolation layer of semiconductor device A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate... | 09/30/2008 |
| 7399679 | Narrow width effect improvement with photoresist plug process and STI corner ion implantation A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the t... | 07/15/2008 |
| 7387942 | Substrate isolation in integrated circuits Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transis... | 06/17/2008 |
| 7371564 | Apparatus for automatically analyzing genetic and protein materials using photodiodes An apparatus for automatically analyzing genetic and protein materials using photodiodes. The apparatus comprises a computer for controlling the entire operation of the apparatus and analyzing a voltage level from a characteristic detector to analyze states of the g... | 05/13/2008 |
| 7361571 | Method for fabricating a trench isolation with spacers A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and ... | 04/22/2008 |
| 7358108 | CMOS image sensor and method for fabricating the same A CMOS image sensor and a method for fabricating the same are disclosed, in which the boundary between an active region and a field region is not damaged by ion implantation. The method for fabricating a CMOS image sensor includes forming a trench in a first conduct... | 04/15/2008 |
| 7358596 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 04/15/2008 |
| 7358105 | Solid-state imaging device, method for manufacturing the same and interline transfer CCD image sensor A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stor... | 04/15/2008 |
| 7358149 | Substrate isolation in integrated circuits Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transis... | 04/15/2008 |
| 7351659 | Methods of forming a transistor with an integrated metal silicide gate electrode Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal si... | 04/01/2008 |
| 7338880 | Method of fabricating a semiconductor device A method of fabricating a semiconductor device includes steps of forming at least one shallow-trench isolation region in a semiconductor substrate; forming a photoresist pattern for blocking a photodiode region; sequentially implanting dopant ions and boron ions int... | 03/04/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7326995 | Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. T... | 02/05/2008 |
| 7304347 | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial l... | 12/04/2007 |
| 7297604 | Semiconductor device having dual isolation structure and method of fabricating the same In a semiconductor device having a dual isolation structure, and a method of fabricating the same, an epitaxial layer is formed on the entire surface of the semiconductor device. A device region including the semiconductor device and the epitaxial layer is defined b... | 11/20/2007 |
| 7294903 | Transistor assemblies Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 11/13/2007 |
| 7291884 | Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the t... | 11/06/2007 |
| 7285497 | Mask, method for manufacturing a mask, method for manufacturing an electro-optical device, and electronic equipment A mask includes a silicon member, and a portion defining an opening penetrating the silicon member; and the corner of the opening is rounded. ... | 10/23/2007 |
| 7285468 | Methods of forming semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 10/23/2007 |
| 7282412 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/16/2007 |
| 7279397 | Shallow trench isolation method A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively p... | 10/09/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7279770 | Isolation techniques for reducing dark current in CMOS image sensors A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate. The first portion has a first width, and the second portion has a second width and is below the first porti... | 10/09/2007 |
| 7276411 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/02/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
