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| Number | Title | Issue Date |
| 8062954 | Method for manufacturing a field plate in a trench of a power transistor A method for manufacturing a field plate in a trench of a power transistor in a substrate of a first conductivity type is disclosed. The trench is formed in a first main surface of the substrate. ... | 11/22/2011 |
| 7560360 | Methods for enhancing trench capacitance and trench capacitor Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first ... | 07/14/2009 |
| 7439156 | Method for manufacturing semiconductor device A semiconductor device and method of manufacturing the same. The method includes: forming a trench in a silicon substrate; forming a first insulating film on a surface of the silicon substrate, the surface including an interior wall of the trench; forming a polysili... | 10/21/2008 |
| 7381625 | Deterministic process for constructing nanodevices A method is provided for constructing a nanodevice. The method includes: fabricating an electrode on a substrate; forming a nanogap across the electrode; dispersing a plurality of nanoobjects onto the substrate using electrophoresis; and pushing one of the nanoobjec... | 06/03/2008 |
| 7371655 | Method of fabricating low-power CMOS device A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The ... | 05/13/2008 |
| 7323530 | Transparent resin film, its manufacturing method, electronic display, liquid crystal display, organic EL display, and touch panel A transparent resin film for an electronic display and its manufacturing method are disclosed, the transparent resin film having an ultraviolet light transmittance of not less than 50%, the ultraviolet light having a wavelength range of from 250 to 450 nm, and havin... | 01/29/2008 |
| 7303961 | Method for producing a junction region between a trench and a semiconductor zone surrounding the trench A method for producing a junction region (2, 5, 6, 7) between a trench (3) and a semiconductor zone (2) surrounding the trench (3) in a trench semiconductor device (1) has the following steps: application of an oxidation barrier la... | 12/04/2007 |
| 7288463 | Pulsed deposition layer gap fill with expansion material Conformal dielectric deposition processes supplemented with a deposited expansion material can fill high aspect ratio narrow width gaps with significantly reduced incidence of voids or weak spots. The technique can also be used generally to form composites, such as ... | 10/30/2007 |
| 7285433 | Integrated devices with optical and electrical isolation and method for making The invention is directed to a method for optical and electrical isolation between adjacent integrated devices. The method comprises the steps of forming at least one trench through an exposed surface of a semiconductor wafer by removing a portion of the semiconduct... | 10/23/2007 |
| 7279396 | Methods of forming trench isolation regions with nitride liner The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is form... | 10/09/2007 |
| 7266787 | Method for optimising transistor performance in integrated circuits A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) bet... | 09/04/2007 |
| 7265054 | Chemical mechanical polishing method for manufacturing semiconductor device Disclosed herein is a chemical mechanical polishing (CMP) method for manufacturing a semiconductor device, comprising performing partial ion implantation of dopants at different concentrations into a plurality of at least two divided regions of a wafer having a plan... | 09/04/2007 |
| 7259074 | Trench isolation method in flash memory device The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer. The present invent... | 08/21/2007 |
| 7235856 | Trench isolation for semiconductor devices In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the no... | 06/26/2007 |
| 7235989 | Electrical test device having isolation slot An electrical test device including a substrate and a plurality of test pads. The test pads are disposed on a second surface of the substrate. Each test pad has a test hole, and first and second isolation slots. The first isolation slot is disposed on the periphery ... | 06/26/2007 |
| 7202184 | Method for fabricating semiconductor device The present invention relates to a semiconductor device fabrication method, which includes forming an inter metal dielectric on a semiconductor substrate having wirings and planarizing the inter metal dielectric through a chemical mechanical polishing, wherein the i... | 04/10/2007 |
| 7176105 | Dielectric gap fill with oxide selectively deposited over silicon liner A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown ... | 02/13/2007 |
| 7173304 | Method of manufacturing devices comprising conductive nano-dots, and devices comprising same A method is disclosed that may include forming a first layer of insulating material above a semiconducting substrate, forming an aluminum oxide layer above the first layer of insulating material, forming a plurality of spaced-apart dots of material on the aluminum o... | 02/06/2007 |
| 7170128 | Multi-bit nanocrystal memory An improved memory cell having a pair of non-volatile memory transistors with each transistor using a nanocrystal gate structure, the transistor pair constructed between a pair of bit line polysilicon depositions. Between the pair of non-volatile memory transistors,... | 01/30/2007 |
| 7109110 | Method of manufacturing a superjunction device A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etche... | 09/19/2006 |
| 7098115 | Semiconductor device and method of manufacturing the same Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method. ... | 08/29/2006 |
| 7087528 | Chemical-mechanical polishing (CMP) process for shallow trench isolation A method of forming shallow trench isolation includes etching trenches through a nitride layer, a polysilicon layer, and a pad oxide layer and into a semiconductor substrate. The trenches are filled with an oxide layer. A silicon oxynitride layer is deposited overly... | 08/08/2006 |
| 7071072 | Forming shallow trench isolation without the use of CMP Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill ... | 07/04/2006 |
| 7064074 | Technique for forming contacts for buried doped regions in a semiconductor device A semiconductor device comprises an isolation trench and a contact trench that may contact a buried conductive region. The contact trench comprises insulating sidewall spacers that are formed during the filling of the isolation trench with an insulating material and... | 06/20/2006 |
| 7060573 | Extended poly buffer STI scheme A new method of forming shallow trench isolations has been described. A silicon semiconductor substrate is provided. A silicon nitride layer is deposited overlying the substrate. A polysilicon layer is deposited overlying the silicon nitride layer. An oxidation mask... | 06/13/2006 |
| 7060629 | Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device A method for etching silicon nitride selective to silicon dioxide and silicon (polycrystalline silicon or monocrystalline silicon) comprises the use of oxygen along with an additional etchant of either CHF3 or CH2F2. Flow rates, powe... | 06/13/2006 |
| 7056805 | Substrate provided with an alignment mark in a substantially transmissive process layer, mask for exposing said mark, device manufacturing method, and device manufactured thereby A method according to one embodiment includes aligning an alignment mark in a substantially transmissive process layer overlying a substrate, said mark comprising high reflectance areas for reflecting radiation of an alignment beam of radiation, and low reflectance ... | 06/06/2006 |
| 7049206 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 05/23/2006 |
| 7043328 | Method for manufacturing semiconductor device utilizing monitor wafers A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present inven... | 05/09/2006 |
| 7029988 | Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon... | 04/18/2006 |
| 7015115 | Method for forming deep trench isolation and related structure According to one embodiment, a structure comprises a substrate and a field oxide region, where the field oxide region has a top surface, and where the top surface of the field oxide region comprises substantially no cavities caused by lateral etching. The structure ... | 03/21/2006 |
| 6960818 | Recessed shallow trench isolation structure nitride liner and method for making same A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling a trench with a photoresist plug and removing a portion of the photor... | 11/01/2005 |
| 6930018 | Shallow trench isolation structure and method Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the fo... | 08/16/2005 |
| 6913984 | Method of manufacturing memory with nano dots A method of fabricating memory with nano dots includes sequentially depositing a first insulating layer, a charge storage layer, a sacrificial layer, and a metal layer on a substrate in which source and drain electrodes are formed, forming a plurality of holes on th... | 07/05/2005 |
| 6911622 | Laser processing The invention provides a system and method for vaporizing a target structure on a substrate. According to the invention, a calculation is performed, as a function of wavelength, of an incident beam energy necessary to deposit unit energy in the target structure. The... | 06/28/2005 |
| 6909150 | Mixed signal integrated circuit with improved isolation An integrated circuit having improved isolation includes a first circuit section formed in a substrate and a second circuit section formed in the substrate, the second circuit section being spaced laterally from the first circuit section. The integrated circuit furt... | 06/21/2005 |
| 6884687 | SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally s... | 04/26/2005 |
| 6878606 | Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon... | 04/12/2005 |
| 6861311 | SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally s... | 03/01/2005 |
| 6838355 | Damascene interconnect structures including etchback for low-k dielectric materials A method for forming back-end-of-line (BEOL) interconnect structures in disclosed. The method and resulting structure includes etchback for low-k dielectric materials. Specifically, a low dielectric constant material is integrated into a dual or single damascene wir... | 01/04/2005 |
