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| Number | Title | Issue Date |
| 8163626 | Enhancing NAND flash floating gate performance Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioni... | 04/24/2012 |
| 8158487 | Annealing process for annealing a structure The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a fir... | 04/17/2012 |
| 7972933 | Method of selective nitridation Methods of forming semiconductor devices are provided herein. In some embodiments, a method of forming a semiconductor device may include providing a substrate having an oxide surface and a silicon surface; forming a nitrogen-containing layer on exposed portions of ... | 07/05/2011 |
| 7939421 | Method for fabricating integrated circuit structures A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the... | 05/10/2011 |
| 7879685 | System and method for creating electric isolation between layers comprising solar cells Methods for forming a patterned layer from common layer in a photovoltaic application are provided. The patterned layer is configured to form one or more portions of one or more solar cells on a rigid substrate. A first pass is made with a first laser beam over an a... | 02/01/2011 |
| 7723205 | Semiconductor device, manufacturing method thereof, liquid crystal display device, RFID tag, light emitting device, and electronic device There is provided a semiconductor device, in which characteristics of the semiconductor device are improved by thinning a gate insulating film and a leak current can be reduced, and a manufacturing method thereof. An aluminum film which is a metal film is formed ove... | 05/25/2010 |
| 7648886 | Shallow trench isolation process A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which redu... | 01/19/2010 |
| 7541259 | Semiconductor device having a compressed device isolation structure The semiconductor device includes a lower device isolation structure formed in a semiconductor substrate to define an active region. The lower device isolation structure has a first compressive stress. An upper device isolation structure is disposed over the lower d... | 06/02/2009 |
| 7479440 | Method of forming an isolation structure that includes forming a silicon layer at a base of the recess A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the ... | 01/20/2009 |
| 7422961 | Method of forming isolation regions for integrated circuits A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which ... | 09/09/2008 |
| 7402886 | Memory with self-aligned trenches for narrow gap isolation regions Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a secon... | 07/22/2008 |
| 7371695 | Use of TEOS oxides in integrated circuit fabrication processes A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask. ... | 05/13/2008 |
| 7371655 | Method of fabricating low-power CMOS device A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The ... | 05/13/2008 |
| 7368342 | Semiconductor device and method of manufacturing the same A method for manufacturing a semiconductor device includes forming a gate-insulating film on a semiconductor substrate; forming a gate electrode on the gate-insulating film to be electrically insulated from the semiconductor substrate; etching the gate electrode, th... | 05/06/2008 |
| 7365362 | Semiconductor device and method of fabricating semiconductor device using oxidation According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising: forming a gate insulating film on a semiconductor substrate; forming a film containing a predetermin... | 04/29/2008 |
| 7361558 | Method of manufacturing a closed cell trench MOSFET Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body regi... | 04/22/2008 |
| 7361560 | Method of manufacturing a dielectric layer in a memory device that includes nitriding step A method for manufacturing a dielectric layer structure for a non-volatile memory cell is provided. A method includes forming a first dielectric layer for tunneling on a semiconductor substrate, a second dielectric layer on the first dielectric layer to store charge... | 04/22/2008 |
| 7361562 | Method of manufacturing semiconductor device Provided is a method of manufacturing a semiconductor device capable of forming a thin high-quality gate oxide layer by suppressing occurrence of recoiled oxygen due to ion implanting. The method of manufacturing a semiconductor device includes steps of: removing an... | 04/22/2008 |
| 7358596 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 04/15/2008 |
| 7319062 | Trench isolation method with an epitaxially grown capping layer A trench isolation method for a semiconductor device, wherein a capping layer formed of an insulating material fills a recess generated at a border edge between an active area and an inactive area. The border edge is defined by a trench filled with insulating materi... | 01/15/2008 |
| 7309641 | Method for rounding bottom corners of trench and shallow trench isolation process A method for rounding the bottom corners of a trench is described. In the method, an etching process is performed using a fluorocarbon compound with at least two carbon atoms, He and O2 as an etching gas to round the bottom corners of the trench. ... | 12/18/2007 |
| 7303961 | Method for producing a junction region between a trench and a semiconductor zone surrounding the trench A method for producing a junction region (2, 5, 6, 7) between a trench (3) and a semiconductor zone (2) surrounding the trench (3) in a trench semiconductor device (1) has the following steps: application of an oxidation barrier la... | 12/04/2007 |
| 7300855 | Reversible oxidation protection of microcomponents In a method for the reversible oxidation protection of microcomponents, a substrate is provided, a silicon nitride layer is provided on the substrate in order to protect it against oxidation, an insulation layer is applied to the silicon nitride layer, and a reoxida... | 11/27/2007 |
| 7300884 | Pattern forming method, underlayer film forming composition, and method of manufacturing semiconductor device According to an aspect of the invention, there is provided a pattern forming method comprising forming an underlayer film on a film to be worked which has been formed on a semiconductor substrate, subjecting the underlayer film to an oxidizing treatment, forming an ... | 11/27/2007 |
| 7294583 | Methods for the use of alkoxysilanol precursors for vapor deposition of SiOfilms A method for depositing conformal dielectric films uses alkoxy silanol or silanediol precursors and oxidizing and/or hydrolyzing agents. The method produces a material with liquid-like flow properties capable of achieving improved high aspect ratio gap fill more eff... | 11/13/2007 |
| 7288463 | Pulsed deposition layer gap fill with expansion material Conformal dielectric deposition processes supplemented with a deposited expansion material can fill high aspect ratio narrow width gaps with significantly reduced incidence of voids or weak spots. The technique can also be used generally to form composites, such as ... | 10/30/2007 |
| 7285433 | Integrated devices with optical and electrical isolation and method for making The invention is directed to a method for optical and electrical isolation between adjacent integrated devices. The method comprises the steps of forming at least one trench through an exposed surface of a semiconductor wafer by removing a portion of the semiconduct... | 10/23/2007 |
| 7279377 | Method and structure for shallow trench isolation during integrated circuit device manufacture A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises etching through silicon nitride and pad oxide layers and into a semiconductor wafer to form a trench into... | 10/09/2007 |
| 7279394 | Method for forming wall oxide layer and isolation layer in flash memory device Disclosed herein are methods for forming wall oxide films in flash memory devices and methods for forming isolation films. After trenches are formed in the substrate, an ISSG (In-Situ Steam Generation) oxidization process is performed to form wall oxide films on sid... | 10/09/2007 |
| 7267037 | Bidirectional singulation saw and method A singulation saw for sawing either substrate or wafers includes a pair of counter-rotating saw blades mounted for independent movement in a vertical direction for alternatively engaging with a substrate to be singulated. The singulation saw further includes a trans... | 09/11/2007 |
| 7265014 | Avoiding field oxide gouging in shallow trench isolation (STI) regions A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI regi... | 09/04/2007 |
| 7262110 | Trench isolation structure and method of formation In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a ... | 08/28/2007 |
| 7259074 | Trench isolation method in flash memory device The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer. The present invent... | 08/21/2007 |
| 7259069 | Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat... | 08/21/2007 |
| 7253065 | Self-aligned nanotube field effect transistor and method of fabricating same A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a... | 08/07/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7238587 | Semiconductor device fabrication method According to the present invention, there is provided a semiconductor device fabrication method that coats a semiconductor substrate with a silazane perhydride polymer solution prepared by dispersing a silazane perhydride polymer in a solvent containing carbon, ther... | 07/03/2007 |
| 7238588 | Silicon buffered shallow trench isolation A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which ... | 07/03/2007 |
| 7235459 | Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ... | 06/26/2007 |
| 7229896 | STI process for eliminating silicon nitride liner induced defects The present invention discloses an improved shallow trench isolation process. A semiconductor substrate having a pad oxide disposed thereon and a pad nitride disposed directly on the pad oxide is provided. A trench is etched, through the pad oxide and the pad nitrid... | 06/12/2007 |
