Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 8183125 | Semiconductor device and manufacturing method A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high resistivity region and at least an insulating structure is provi... | 05/22/2012 |
| 8058140 | Thickened sidewall dielectric for memory cell Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielec... | 11/15/2011 |
| 8043933 | Integration sequences with top surface profile modification Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to apparatus and methods for forming shallow trench isolations having recesses wit... | 10/25/2011 |
| 8039359 | Method of forming low capacitance ESD device and structure therefor In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage. ... | 10/18/2011 |
| 8012848 | Trench isolation and method of fabricating trench isolation Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer ov... | 09/06/2011 |
| 8003488 | Shallow trench isolation structure compatible with SOI embedded DRAM A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of t... | 08/23/2011 |
| 7960244 | Process for the aligned manufacture of electronic semiconductor devices in a SOI substrate A process for manufacturing an electronic semiconductor device, wherein a SOI wafer is provided, formed by a bottom layer of semiconductor material, an insulating layer, and a top layer of semiconductor material, stacked on top of one another; alignment marks are fo... | 06/14/2011 |
| 7939420 | Processes for forming isolation structures for integrated circuit devices Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In ano... | 05/10/2011 |
| 7927967 | Method for manufacturing semiconductor memory device A method for manufacturing a semiconductor memory device, includes: forming a stacked unit above a semiconductor substrate; making a hole in the stacked unit to pass through electrode layers and insulating layers of the stacked unit; forming an insulating film on a ... | 04/19/2011 |
| 7851327 | Method of manufacturing a semiconductor device including forming a single-crystalline semiconductor material in a first area and forming a second device isolation pattern on a second area In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first ins... | 12/14/2010 |
| 7833876 | Semiconductor device having multiple element formation regions and manufacturing method thereof In a manufacturing of a semiconductor device, at least one of elements is formed in each of element formation regions of a substrate having a main side and a rear side, and the substrate is thinned by polished from a rear side of the substrate, and then, multiple tr... | 11/16/2010 |
| 7816229 | Semiconductor device with channel stop trench and method A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the chann... | 10/19/2010 |
| 7811897 | Method of forming trench isolation A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed to an aqueous liquid etching solution comprising a hydroxide and a fluoride, and having a pH of at least... | 10/12/2010 |
| 7795109 | Isolation trenches with conductive plates Methods of forming isolation trenches, semiconductor devices, structures thereof, and methods of operating memory arrays are disclosed. In one embodiment, an isolation trench includes a recess disposed in a workpiece. A conductive material is disposed in a lower por... | 09/14/2010 |
| 7723204 | Semiconductor device with a multi-plate isolation structure A microelectronic assembly and a method for constructing a microelectronic assembly are provided. The microelectronic assembly may include a semiconductor substrate with an isolation trench (62) formed therein. The isolation trench (62) may have first ... | 05/25/2010 |
| 7713834 | Method of forming isolation regions for integrated circuits A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which ... | 05/11/2010 |
| 7704853 | Method for the elimination of the effects of defects on wafers A method eliminates effects of defects on wafers caused by cavities adjacent to the surface of a semiconductor (e.g., silicon) wafer. A first insulating layer is applied to the surface of the semiconductor wafer and into the cavities adjacent to the surface. The app... | 04/27/2010 |
| 7704854 | Method for fabricating semiconductor device having conductive liner for rad hard total dose immunity The invention relates to a method includes etching at least one shallow trench in at least an SIO layer; forming a dielectric liner at an interface of the SIO layer and the SIO layer; forming a metal or metal alloy layer in the shallow trench on the dielectric liner... | 04/27/2010 |
| 7468307 | Semiconductor structure and method A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed ... | 12/23/2008 |
| 7462550 | Method of forming a trench semiconductor device and structure therefor In one embodiment, a trench semiconductor device is formed to have an oxide of a first thickness along the sidewalls of the trench, and to have a greater thickness along at least a portion of a bottom of the trench. ... | 12/09/2008 |
| 7442619 | Method of forming substantially L-shaped silicide contact for a semiconductor device A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In... | 10/28/2008 |
| 7439156 | Method for manufacturing semiconductor device A semiconductor device and method of manufacturing the same. The method includes: forming a trench in a silicon substrate; forming a first insulating film on a surface of the silicon substrate, the surface including an interior wall of the trench; forming a polysili... | 10/21/2008 |
| 7439421 | Soybean variety XB22N06 According to the invention, there is provided a novel soybean variety designated XB22N06. This invention thus relates to the seeds of soybean variety XB22N06, to the plants of soybean XB22N06 to plant parts of soybean variety XB22N06 and to methods for producing a s... | 10/21/2008 |
| 7432173 | Methods of fabricating silicon-on-insulator substrates having a laser-formed single crystalline film In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor... | 10/07/2008 |
| 7432605 | Overlay mark, method for forming the same and application thereof An overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer is described, including a part of the lower layer having two first x-directional trenches, two first y-directional trenches, two second x-... | 10/07/2008 |
| 7425486 | Method for forming a trench capacitor A method for forming a trench capacitor is presented in the following process steps. A trench is formed on a semiconductor substrate. A first trench dielectric is deposited into the trench without reaching a full height thereof. An etch stop layer is formed on the f... | 09/16/2008 |
| 7419611 | Processes and materials for step and flash imprint lithography A method of forming an image. The method includes: a transfer layer on a substrate; forming on the transfer layer, an etch barrier layer; pressing a template having a relief pattern into the etch barrier layer; exposing the etch barrier layer to actinic radiation fo... | 09/02/2008 |
| 7416937 | Semiconductor device and method for fabricating the same A method creates semiconductor device in which a storage dielectric film and a storage electrode included in the capacitor is transferred from an inactive region of a semiconductor substrate to the active region thereof, i.e., into a device isolating trench such tha... | 08/26/2008 |
| 7416947 | Method of fabricating trench MIS device with thick oxide layer in bottom of trench A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectr... | 08/26/2008 |
| 7413961 | Method of fabricating a transistor structure The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provi... | 08/19/2008 |
| 7410881 | Method of manufacturing flash memory device A method of manufacturing a flash memory device includes etching an insulating layer provided over a substrate to form a contact hole to define a contact hole exposing a junction region formed on the substrate. The contact hole is filled with a first conductive mate... | 08/12/2008 |
| 7396739 | Method for integrating an electronic component or similar into a substrate A method for integrating an electronic component or the like into a substrate includes following process steps: formation of a dielectric insulating layer on the front side of a substrate; complete back-etching of an area of the substrate from the back of the substr... | 07/08/2008 |
| 7394144 | Trench semiconductor device and method of manufacturing it Consistent with an example embodiment, a reduced surface field effect type (RESURF) semiconductor device is manufactured having a drift region over a drain region. Trenches are formed through openings in mask. A trench insulating layer is deposited on the sidewalls ... | 07/01/2008 |
| 7387907 | Image sensor with optical guard ring and fabrication method thereof An image sensor device and fabrication method thereof wherein a substrate having at least one shallow trench isolation structure therein is provided. At least one photosensor and at least one light emitting element, e.g., such as MOS or LED, are formed in the substr... | 06/17/2008 |
| 7371655 | Method of fabricating low-power CMOS device A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The ... | 05/13/2008 |
| 7371657 | Method for forming an isolating trench with a dielectric material The present invention relates to a method of forming an isolating trench of a semiconductor device with a dielectric material, and to a method of forming an isolating trench in a memory device. ... | 05/13/2008 |
| 7371607 | Method of manufacturing semiconductor device and method of manufacturing electronic device A method of manufacturing a semiconductor device includes mounting a first semiconductor chip on each partitioned region of a frame substrate partitioned for each first semiconductor package; mounting a second semiconductor package, where a second semiconductor chip... | 05/13/2008 |
| 7358144 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first... | 04/15/2008 |
| 7358596 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 04/15/2008 |
| 7358558 | Flash memory device A floating gate of a flash memory device is formed in a moat formed in an isolation film. Therefore, an electric field applied between a control gate and a channel region upon cycling can be precluded or mitigated. A distance between the control gate and the channel... | 04/15/2008 |
