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| Number | Title | Issue Date |
| 8133797 | Protective layer to enable damage free gap fill In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids ... | 03/13/2012 |
| 8017495 | Method of forming isolation layer structure and method of manufacturing a semiconductor device including the same An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in... | 09/13/2011 |
| 8012847 | Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is de... | 09/06/2011 |
| 8003487 | Methods of manufacturing a semiconductor device using a layer suspended across a trench In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the fir... | 08/23/2011 |
| 7989309 | Method of improving a shallow trench isolation gapfill process A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally... | 08/02/2011 |
| 7977205 | Method of forming isolation layer of semiconductor device A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a... | 07/12/2011 |
| 7943483 | Method of manufacturing semiconductor device In forming an element isolation trench, an insulating film formed above a semiconductor substrate is etched such that relatively thin insulating film situated in the memory cell region is fully removed whereas relatively thick insulating film situated in the periphe... | 05/17/2011 |
| 7939419 | Method of filling a trench in a substrate A method of filling a trench includes: providing a substrate having an upper surface, and a trench extending therein from the upper surface; forming a deposition layer on the substrate in a manner in which the layer partially fills the trench and has a portion which... | 05/10/2011 |
| 7935610 | Semiconductor device isolation structures Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a second integrated device region on a substrate that is spaced apart from a first integrated device region. ... | 05/03/2011 |
| 7927966 | Method of manufacturing openings in a substrate, a via in substrate, and a semiconductor device comprising such a via The invention relates to a method of manufacturing openings in a substrate (5), the method comprising steps of: providing the substrate (5) with a masking layer (40) on a surface thereof; forming a first opening (10), a second opening ( | 04/19/2011 |
| 7923346 | Field effect transistor structure with an insulating layer at the junction A method of making a FET includes forming a gate structure (18), then etching cavities on either side. A SiGe layer (22) is then deposited on the substrate (10) in the cavities, followed by an Si layer (24). A selective etch is then carri... | 04/12/2011 |
| 7919389 | Semiconductor memory device that is resistant to high voltages and a method of manufacturing the same A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve ... | 04/05/2011 |
| 7902036 | Method of fabricating semiconductor device and the semiconductor device A method of fabricating a semiconductor device includes forming trench-like recesses in a semiconductor substrate, the recesses including one or more recesses each of which has an opening width of not more than a predetermined value, forming a first insulating film ... | 03/08/2011 |
| 7858490 | Semiconductor device having dual-STI and manufacturing method thereof A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory ... | 12/28/2010 |
| 7851326 | Method for producing deep trench structures A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler m... | 12/14/2010 |
| 7785983 | Semiconductor device having tiles for dual-trench integration and method therefor A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are differen... | 08/31/2010 |
| 7781304 | Semiconductor device having trench isolation region and methods of fabricating the same A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate... | 08/24/2010 |
| 7763524 | Method for forming isolation structure of different widths in semiconductor device A method for forming an isolation structure in a semiconductor device including a substrate having a first region and a second region, the second region having an isolation structure formed to a larger width than a plurality of isolation structures formed in the fir... | 07/27/2010 |
| 7736991 | Method of forming isolation layer of semiconductor device A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region be... | 06/15/2010 |
| 7691722 | Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride lay... | 04/06/2010 |
| 7678664 | Method for fabricating semiconductor device According to a fabrication method for an element isolation structure section, that is, STI, of the present invention, by differing the etching rate of material to be embedded in a narrow-width, that is, a small area trench section (first trench section) formed in a ... | 03/16/2010 |
| 7678663 | Non-volatile semiconductor memory device and method of manufacturing the same A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulat... | 03/16/2010 |
| 7674685 | Semiconductor device isolation structures and methods of fabricating such structures Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the de... | 03/09/2010 |
| 7670925 | Semiconductor device, method of manufacturing same, and apparatus for designing same A semiconductor device is disclosed that includes multiple logic circuit cells having respective logic circuits formed therein; and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed the... | 03/02/2010 |
| 7662697 | Method of forming isolation structure of semiconductor device A method of forming a semiconductor device includes etching a semiconductor substrate to form a first trench having a first width and a first depth; etching the semiconductor substrate to form a second trench having a second width and a second depth, the second tren... | 02/16/2010 |
| 7651922 | Semiconductor device fabrication method A method for fabricating a semiconductor device, includes forming a silicon nitride film on a base body, forming a silicon film on said silicon nitride film, forming at least one groove extending from said silicon film to inside of said base body, forming by high-de... | 01/26/2010 |
| 7622360 | Shallow trench isolation region in semiconductor device and method of manufacture A method of forming a device isolation region in a semiconductor device is capable of completely removing an oxide layer for trench formation in a central region of the semiconductor device without forming a moat in an edge region. The method begins with forming a s... | 11/24/2009 |
| 7595254 | Method of manufacturing a semiconductor device Embodiments relate to a method for manufacturing a semiconductor device, which may reduce damage due to stress of an STI bottom corner during an ion implantation and annealing being subsequent process of an STI in a semiconductor process are provided. According to e... | 09/29/2009 |
| 7547610 | Method of making a semiconductor device comprising isolation trenches inducing different types of strain By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stres... | 06/16/2009 |
| 7544582 | Semiconductor device and method for fabricating the same A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substra... | 06/09/2009 |
| 7521333 | Methods of fabricating trench isolation structures having varying depth A device isolation structure of semiconductor device includes a semiconductor substrate having a cell region, a low voltage region and a high voltage region defined therein. A cell trench isolation region is disposed in the cell region. A low voltage trench isolatio... | 04/21/2009 |
| 7485544 | Strained semiconductor, devices and systems and methods of formation In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regio... | 02/03/2009 |
| 7470597 | Method of fabricating a multilayered dielectric diffusion barrier layer A method of fabricating a structure including a low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer is described herein. The method includes applying a coating of a polymeric preceramic precu... | 12/30/2008 |
| 7439604 | Method of forming dual gate dielectric layer A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer ... | 10/21/2008 |
| 7427553 | Fabricating method of semiconductor device A fabricating method of a semiconductor device is provided. The method comprises the steps of preparing a semiconductor substrate having an active area with a high voltage device area and a low voltage device area and an inactive area, forming a trench in the inacti... | 09/23/2008 |
| 7420259 | Semiconductor device having two-layered charge storage electrode A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in... | 09/02/2008 |
| 7419878 | Planarized and silicided trench contact Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures i... | 09/02/2008 |
| 7416956 | Self-aligned trench filling for narrow gap isolation regions Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a secon... | 08/26/2008 |
| 7396738 | Method of forming isolation structure of flash memory device A method of forming a semiconductor memory device includes providing a semiconductor substrate having a cell region and a peripheral region. A gate dielectric layer is formed over the semiconductor substrate in the peripheral region. An insulating layer is formed ov... | 07/08/2008 |
| 7396728 | Methods of improving drive currents by employing strain inducing STI liners A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defi... | 07/08/2008 |
