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| Number | Title | Issue Date |
| 7816228 | Method of manufacturing a semiconductor device In a method of manufacturing a semiconductor device including a planar type transistor and a fin type transistor, a substrate having a first region and a second region is partially to form an isolation trench defining an isolation region and an active region. An ins... | 10/19/2010 |
| 7803692 | Manufacturing method of semiconductor device having self-aligned contact A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the... | 09/28/2010 |
| 7795108 | Resistance-based etch depth determination for SGT technology A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is p... | 09/14/2010 |
| 7732298 | Metal salicide formation having nitride liner to reduce silicide stringer and encroachment Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other die... | 06/08/2010 |
| 7611963 | Method for forming a multi-layer shallow trench isolation structure in a semiconductor device A method for forming a multi-layer shallow trench isolation structure in a semiconductor device is described. In one embodiment, the method includes etching a shallow trench in a silicon substrate of a semiconductor device and forming a dielectric liner layer on a f... | 11/03/2009 |
| 7563689 | Method for fabricating nonvolatile memory device A method for fabricating a nonvolatile memory device includes forming a gate insulation layer, a first gate conductive layer, a first sacrificial layer, and a second sacrificial layer over a substrate, etching the first and second sacrificial layers, the first gate ... | 07/21/2009 |
| 7560359 | Methods of forming asymmetric recesses and gate structures that fill such recesses and related methods of forming semiconductor devices that include such recesses and gate structures In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufac... | 07/14/2009 |
| 7550364 | Stress engineering using dual pad nitride with selective SOI device architecture A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensil... | 06/23/2009 |
| 7521332 | Resistance-based etch depth determination for SGT technology A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is p... | 04/21/2009 |
| 7449392 | Semiconductor device capable of threshold voltage adjustment by applying an external voltage A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surfa... | 11/11/2008 |
| 7439604 | Method of forming dual gate dielectric layer A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer ... | 10/21/2008 |
| 7439421 | Soybean variety XB22N06 According to the invention, there is provided a novel soybean variety designated XB22N06. This invention thus relates to the seeds of soybean variety XB22N06, to the plants of soybean XB22N06 to plant parts of soybean variety XB22N06 and to methods for producing a s... | 10/21/2008 |
| 7432172 | Plasma etching method A plasma etching method for etching an object to be processed, which has at least an etching target layer and a patterned mask layer formed on the etching target layer, to form a recess corresponding to a pattern of the mask layer in the etching target layer, includ... | 10/07/2008 |
| 7427515 | Electronic element including ferroelectric substance film and method of manufacturing the same A laminated film structure, method of manufacturing, and a preferable electronic element using the structure. The effective polarization into the electric field can be realized in the direction of crystal axis by enhancing the crystal property and alignment property... | 09/23/2008 |
| 7427553 | Fabricating method of semiconductor device A fabricating method of a semiconductor device is provided. The method comprises the steps of preparing a semiconductor substrate having an active area with a high voltage device area and a low voltage device area and an inactive area, forming a trench in the inacti... | 09/23/2008 |
| 7425495 | Method of manufacturing semiconductor substrate and semiconductor device A method of manufacturing a semiconductor substrate and semiconductor device is disclosed and comprises forming a first monocrystalline semiconductor layer on a semiconductor base material, forming a second monocrystalline semiconductor layer covering the first mono... | 09/16/2008 |
| 7422960 | Method of forming gate arrays on a partial SOI substrate The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. Th... | 09/09/2008 |
| 7416956 | Self-aligned trench filling for narrow gap isolation regions Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a secon... | 08/26/2008 |
| 7410891 | Method of manufacturing a superjunction device A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etche... | 08/12/2008 |
| 7402498 | Methods of forming trench isolation regions The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is form... | 07/22/2008 |
| 7396729 | Methods of forming semiconductor devices having a trench with beveled corners A semiconductor device is formed by providing a substrate. A trench is formed in the substrate. Beveled surfaces are formed at upper portions of sidewalls of the trench opposite a bottom surface of the trench, respectively. An oxide layer is formed in the trench suc... | 07/08/2008 |
| 7396738 | Method of forming isolation structure of flash memory device A method of forming a semiconductor memory device includes providing a semiconductor substrate having a cell region and a peripheral region. A gate dielectric layer is formed over the semiconductor substrate in the peripheral region. An insulating layer is formed ov... | 07/08/2008 |
| 7396732 | Formation of deep trench airgaps and related applications A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfille... | 07/08/2008 |
| 7358191 | Method for decreasing sheet resistivity variations of an interconnect metal layer According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenche... | 04/15/2008 |
| 7358596 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 04/15/2008 |
| 7339252 | Semiconductor having thick dielectric regions A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second... | 03/04/2008 |
| 7339242 | NAND-type flash memory devices and fabrication methods thereof In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interc... | 03/04/2008 |
| 7335583 | Isolating semiconductor device structures An array of continuous diffusion regions and continuous gate electrode structures is formed over a semiconductor substrate. Interconnecting diffusion region portions and interconnecting gate electrode portions are removed to electrically isolate transistor circuitry... | 02/26/2008 |
| 7320926 | Shallow trench filled with two or more dielectrics for isolation and coupling for stress control A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and fi... | 01/22/2008 |
| 7319062 | Trench isolation method with an epitaxially grown capping layer A trench isolation method for a semiconductor device, wherein a capping layer formed of an insulating material fills a recess generated at a border edge between an active area and an inactive area. The border edge is defined by a trench filled with insulating materi... | 01/15/2008 |
| 7303951 | Method of manufacturing a trench isolation region in a semiconductor device A method of manufacturing a semiconductor device for preventing dielectric breakdown of gate electrodes attributable to needle-like protrusions caused inside a trench in the step of forming element isolation trench in which includes forming a silicon oxide film over... | 12/04/2007 |
| 7301207 | Semiconductor device capable of threshold voltage adjustment by applying an external voltage A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surfa... | 11/27/2007 |
| 7294536 | Process for manufacturing an SOI wafer by annealing and oxidation of buried channels A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.... | 11/13/2007 |
| 7291540 | Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using SOI wafers The invention is directed to a hermetically packaged and implantable integrated circuit for electronics that is made my producing streets in silicon-on-insulator chips that are subsequently coated with a selected electrically insulating thin film prior to completing... | 11/06/2007 |
| 7279396 | Methods of forming trench isolation regions with nitride liner The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is form... | 10/09/2007 |
| 7276774 | Trench isolation structures for integrated circuits A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no mo... | 10/02/2007 |
| 7276411 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/02/2007 |
| 7267037 | Bidirectional singulation saw and method A singulation saw for sawing either substrate or wafers includes a pair of counter-rotating saw blades mounted for independent movement in a vertical direction for alternatively engaging with a substrate to be singulated. The singulation saw further includes a trans... | 09/11/2007 |
| 7265022 | Method of fabricating semiconductor device with STI structure A method of fabricating a semiconductor device, includes depositing, on a semiconductor substrate, a gate insulating film, a polycrystalline or amorphous silicon film, a silicon nitride film and a silicon oxide film sequentially, patterning a resist for forming a pl... | 09/04/2007 |
| 7247567 | Method of polishing a tungsten-containing substrate The invention provides a method of chemically-mechanically polishing a substrate comprising tungsten through use of a composition comprising a tungsten etchant, an inhibitor of tungsten etching, and water, wherein the inhibitor of tungsten polishing is a polymer, co... | 07/24/2007 |
