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| Number | Title | Issue Date |
| 8071460 | Method for manufacturing semiconductor device In a method of manufacturing a semiconductor device, a first film is formed directly on a semiconductor substrate and a second film is formed on the first film. A region of the second film is then etched to form an opening that exposes the first film. The first film... | 12/06/2011 |
| 8071461 | Low loss substrate for integrated passive devices Electronic elements (44, 44′, 44″) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62′, 62″) in the IPD re... | 12/06/2011 |
| 8048764 | Dual etch method of defining active area in semiconductor device A method of forming a hardmask for defining shallow trench isolation regions in a semiconductor substrate layer includes the steps of: depositing a hardmask layer over the semiconductor substrate layer; depositing and patterning a first photoresist layer over the ha... | 11/01/2011 |
| 8039358 | Method of manufacturing semiconductor device on which a plurality of types of transistors are mounted A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and se... | 10/18/2011 |
| 8030171 | Method of forming element isolation film and nonvolatile semiconductor memory An element isolation film is formed by filling an oxide in a trench formed in an element isolation region of a semiconductor substrate to thereby form an insulation film for element isolation. A method of forming the element isolation film includes a first step of d... | 10/04/2011 |
| 8017494 | Termination trench structure for mosgated device and process for its manufacture A process for the fabrication of a MOSgated device that includes a plurality of spaced trenches in the termination region thereof. ... | 09/13/2011 |
| 7989308 | Creation of dielectrically insulating soi-technlogical trenches comprising rounded edges for allowing higher voltages The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenche... | 08/02/2011 |
| 7943482 | Method for semiconductor device having radiation hardened insulators and design structure thereof A design structure is provided for a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The device includes a first structure and a second structure. The first structure includes: a radiation hardened BOX lay... | 05/17/2011 |
| 7935609 | Method for fabricating semiconductor device having radiation hardened insulators A method is provided for fabricating a semiconductor device and more particularly to a method of manufacturing a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The method includes removing a substrate fro... | 05/03/2011 |
| 7858489 | Method for manufacturing semiconductor device capable of increasing current drivability of PMOS transistor A semiconductor device capable of selectively applying different stresses for increasing current drivability of PMOS transistor is made by defining trenches in a semiconductor substrate having a PMOS region; forming selectively a buffer layer on sidewalls of the tre... | 12/28/2010 |
| RE41696 | Semiconductor device and manufacturing method thereof The present invention provides a semiconductor device that reduces the junction leak current and achieves an improvement in the reliability of the gate oxide film by minimizing divot formation and the occurrence of a kink and a method of manufacturing such a semicon... | 09/14/2010 |
| 7772084 | Process for self-aligned manufacture of integrated electronic devices A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats th... | 08/10/2010 |
| 7763523 | Method for forming device isolation structure of semiconductor device using annealing steps to anneal flowable insulation layer A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having acti... | 07/27/2010 |
| 7696061 | Semiconductor device and method for manufacturing same A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region fo... | 04/13/2010 |
| 7691721 | Method for manufacturing flash memory device Provided is a method for manufacturing a flash memory device, in which an oxidation process is carried out on the disclosed top surface of a semiconductor substrate to form a surface oxide film in the form of bird's beak with an appropriate width before conducting a... | 04/06/2010 |
| 7682929 | Method and structure for double lining for shallow trench isolation A method of forming an integrated circuit device structure having a design rule of less than 0.13 micron. The method includes providing a substrate and forming a pad oxide layer overlying the substrate. The method includes forming a nitride layer overlying the pad o... | 03/23/2010 |
| 7625807 | Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner... | 12/01/2009 |
| 7608518 | Semiconductor device and method for fabricating the same A method for fabricating a semiconductor device is provided. The method includes forming a pad oxide layer on a semiconductor substrate, forming a pad nitride layer on the pad oxide layer, forming a capping layer on the pad nitride layer, patterning the capping laye... | 10/27/2009 |
| 7553741 | Manufacturing method of semiconductor device Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteris... | 06/30/2009 |
| 7473615 | Semiconductor processing methods The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present... | 01/06/2009 |
| 7439158 | Strained semiconductor by full wafer bonding One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonde... | 10/21/2008 |
| 7432172 | Plasma etching method A plasma etching method for etching an object to be processed, which has at least an etching target layer and a patterned mask layer formed on the etching target layer, to form a recess corresponding to a pattern of the mask layer in the etching target layer, includ... | 10/07/2008 |
| 7427553 | Fabricating method of semiconductor device A fabricating method of a semiconductor device is provided. The method comprises the steps of preparing a semiconductor substrate having an active area with a high voltage device area and a low voltage device area and an inactive area, forming a trench in the inacti... | 09/23/2008 |
| 7419878 | Planarized and silicided trench contact Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures i... | 09/02/2008 |
| 7416956 | Self-aligned trench filling for narrow gap isolation regions Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a secon... | 08/26/2008 |
| 7402473 | Semiconductor device and process for producing the same A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around th... | 07/22/2008 |
| 7381631 | Use of expanding material oxides for nano-fabrication This invention relates to a method of fabricating nano-dimensional structures, comprising: depositing at least one deformable material upon a substrate such that the material includes at least one portion; and creating an oxidizable layer located substantially adjac... | 06/03/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7361571 | Method for fabricating a trench isolation with spacers A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and ... | 04/22/2008 |
| 7358588 | Trench isolation type semiconductor device which prevents a recess from being formed in a field region A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active ... | 04/15/2008 |
| 7358596 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 04/15/2008 |
| 7332399 | Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor in which film thicknesses can be accurately controlled A method of manufacturing semiconductor substrates. After supporting layers are provided on side walls of grooves formed in a semiconductor substrate, grooves that expose a second semiconductor layer are formed. Etching gas or etching liquid is brought in contact wi... | 02/19/2008 |
| 7326625 | Trench structure having a void and inductor including the trench structure In a method of forming a trench structure having a wide void therein, a first trench having a first width and a first depth is formed in a substrate. The first trench is filled with a first insulation layer pattern defining the void in the first trench. A second tre... | 02/05/2008 |
| 7326621 | Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After formin... | 02/05/2008 |
| 7323394 | Method of producing element separation structure A method of producing an element separation structure includes the steps of: forming a first thermal oxide film on the substrate; forming a silicon nitride film on the first thermal oxide film; removing the first thermal oxide film and the silicon nitride film in an... | 01/29/2008 |
| 7321141 | Image sensor device and manufacturing method thereof A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. T... | 01/22/2008 |
| 7320926 | Shallow trench filled with two or more dielectrics for isolation and coupling for stress control A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and fi... | 01/22/2008 |
| 7319252 | Methods for forming semiconductor wires and resulting devices Methods for forming a wire from silicon or other semiconductor material are disclosed. Also disclosed are various devices including such a semiconductor wire. According to one embodiment, a wire is spaced apart from an underlying substrate, and the wire extends betw... | 01/15/2008 |
| 7316979 | Method and apparatus for providing an integrated active region on silicon-on-insulator devices A method and apparatus for providing integrated active regions on silicon-on-insulator (SOI) devices by oxidizing a portion of the active layer. When the active layer of the SOI wafer is relatively thick, such as about 200 Å to 1000 Å or greater, the etching pro... | 01/08/2008 |
| 7314792 | Method for fabricating transistor of semiconductor device A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to fo... | 01/01/2008 |
