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| Number | Title | Issue Date |
| 8187949 | Semiconductor device and method of manufacturing the same When a thin semiconductor device is formed by grinding a wafer, it has been necessary to dice the wafer into dies and process the back surfaces of the dies separately. In the invention, a wafer 2a is half-diced from the front surface thereof to form gr... | 05/29/2012 |
| 8187948 | Hybrid gap-fill approach for STI formation A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition... | 05/29/2012 |
| 8183124 | Silicon carbide and related wide-bandgap transistors on semi insulating epitaxy A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and g... | 05/22/2012 |
| 8178417 | Method of forming shallow trench isolation structures for integrated circuits A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings ... | 05/15/2012 |
| 8173514 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties... | 05/08/2012 |
| 8168508 | Method of isolating nanowires from a substrate A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of n... | 05/01/2012 |
| 8163625 | Method for fabricating an isolation structure The disclosure relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure having almost no divot. An exemplary method for fabricating an isolation structure, comprising: forming a pad oxide layer over a top s... | 04/24/2012 |
| 8163624 | Discrete semiconductor device and method of forming sealed trench junction termination A discrete semiconductor device has a substrate with a first conductivity type of semiconductor material. A first semiconductor layer is formed over the substrate. The first semiconductor layer having the first conductivity type of semiconductor material. A second s... | 04/24/2012 |
| 8158486 | Trench isolation structure having different stress By locally heating isolation trenches with different annealing conditions, a different magnitude of intrinsic stress may be obtained in different isolation trenches. In some illustrative embodiments, the different anneal temperature may be achieved on the basis of a... | 04/17/2012 |
| 8153501 | Maskless selective boron-doped epitaxial growth A semiconductor device, comprising a silicon layer, an n-type field-effect transistor (NFET) disposed in and on a silicon layer, and a p-type field-effect transistor (PFET) disposed in and on the silicon layer, wherein the PFET includes a boron-doped silicon-germani... | 04/10/2012 |
| 8143137 | Method of fabricating semiconductor device by thinning hardmask layers on frontside and backside of substrate The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontsid... | 03/27/2012 |
| 8138059 | Semiconductor device manufacturing method A semiconductor device manufacturing method includes: forming a core pattern on a foundation film, the core pattern containing a material generating acid by light exposure; selectively exposing part of the core pattern except an longitudinal end portion; supplying a... | 03/20/2012 |
| 8133796 | Method for fabricating shallow trench isolation structures A method for fabricating shallow trench isolation structures is provided. A patterned pad layer and a patterned mask layer are sequentially formed on a substrate, wherein the substrate includes a memory region and a periphery region. By using the patterned mask laye... | 03/13/2012 |
| 8133795 | Method of manufacturing semiconductor integrated circuit device In the present invention, in the exposure to light of a memory cell array or the like of a semiconductor memory or the like, when a group of unit openings for etching the STI trench regions in which the unit openings for etching the STI trench regions each having a ... | 03/13/2012 |
| 8129253 | Providing current control over wafer borne semiconductor devices using trenches Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1500) having a substrate (1520), at least one active layer (1565) and a surface layer (1510), and electrical contacts (1515) formed on sa... | 03/06/2012 |
| 8119495 | Method of manufacturing a semiconductor device having an active region and dummy patterns There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be place... | 02/21/2012 |
| 8101497 | Self-aligned trench formation Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. ... | 01/24/2012 |
| 8097522 | Modular methods of forming isolation structures for integrated circuits A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be ... | 01/17/2012 |
| 8067292 | Isolation structure, non-volatile memory having the same, and method of fabricating the same A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the diel... | 11/29/2011 |
| 8062951 | Method to increase effective MOSFET width An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a crystal orientation. A... | 11/22/2011 |
| 8062952 | Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors In advanced SOI devices, a high tensile strain component may be achieved on the basis of a globally strained semiconductor layer, while at the same time a certain compressive strain may be induced in P-channel transistors by appropriately selecting a height-to-lengt... | 11/22/2011 |
| 8058139 | Manufacturing method for semiconductor devices A polysilazane perhydride solution, prepared by dispensing polysilazane perhydride in a solvent containing carbon, is applied on a semiconductor substrate (1), thereby forming a coated film (6), which is heated, volatilizing solvent therein, thereby fo... | 11/15/2011 |
| 8053328 | Methods of selective deposition of fine particles onto selected regions of a substrate A method for depositing fine particles from a suspension on selected regions of a substrate is disclosed. The particles are deposited on selected regions of a clean hydrophobic semiconductor surface that are surrounded by a wetting boundary which includes a mesa for... | 11/08/2011 |
| 8048761 | Fabricating method for crack stop structure enhancement of integrated circuit seal ring An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulati... | 11/01/2011 |
| 8048763 | Semiconductor device manufacturing method A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substr... | 11/01/2011 |
| 8048762 | Manufacturing method of semiconductor device A manufacturing method for a semiconductor device includes: forming a first layer on a member to be etched; forming a first hard mask that includes a first hard mask pattern, in the first layer; forming a second layer on the first hard mask and on an exposed surface... | 11/01/2011 |
| 8043932 | Method of fabricating semiconductor device A method of fabricating a semiconductor device including at least one of the following steps: forming an oxide layer on and/or over a silicon substrate. Forming a first photoresist pattern on and/or over the oxide layer. Forming a trench by etching the oxide layer a... | 10/25/2011 |
| 8030170 | Methods of forming isolation structures, and methods of forming nonvolatile memory Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam expo... | 10/04/2011 |
| 8026151 | Method with high gapfill capability for semiconductor devices A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, w... | 09/27/2011 |
| 8021956 | Ultrathin SOI CMOS devices employing differential STI liners An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking... | 09/20/2011 |
| 8021955 | Method characterizing materials for a trench isolation structure having low trench parasitic capacitance Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper... | 09/20/2011 |
| 8021957 | Process of forming an electronic device including insulating layers having different strains An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating laye... | 09/20/2011 |
| 8017493 | Method of planarizing a semiconductor device A process of forming a semiconductor process fabricated device which contains a trench, hole or gap filled with a conformally deposited material is disclosed. A sacrificial planarizing layer is formed on the fill material, and the device is planarized using a select... | 09/13/2011 |
| 8012846 | Isolation structures and methods of fabricating isolation structures A method of forming an isolation structure includes the steps of: (a) forming an opening within a substrate; (b) forming a substantially conformal layer comprising tetraethoxysilane (TEOS) layer along the opening; and (c) forming a dielectric layer over the TEOS lay... | 09/06/2011 |
| 8008163 | Method of fabricating semiconductor device A method of fabricating a semiconductor device, the method including forming a buffer oxide layer in a first region and a second region of a semiconductor substrate; forming a plurality of first preliminary mask patterns on the buffer oxide layer in the first region... | 08/30/2011 |
| 8003485 | Semiconductor device and method of fabricating the same In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried ... | 08/23/2011 |
| 8003486 | Method of making a semiconductor device having a strained semiconductor active region using edge relaxation, a buried stressor layer and a sacrificial stressor layer The present invention relates to creating an active layer of strained semiconductor using a combination of buried and sacrificial stressors. That is, a process can strain an active semiconductor layer by transferring strain from a stressor layer buried below the act... | 08/23/2011 |
| 7998830 | Semiconductor device with both I/O and core components and method of fabricating same A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate an... | 08/16/2011 |
| 7998829 | Semiconductor structure and method of manufacture In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an electrochemical etch to form a first cavity, a second cavity, whe... | 08/16/2011 |
| 7989307 | Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlin... | 08/02/2011 |
