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| Number | Title | Issue Date |
| 8129252 | Semiconductor devices with sealed, unlined trenches and methods of forming same A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor m... | 03/06/2012 |
| 8067291 | MOS field-effect transistor and manufacturing method thereof To provide a manufacturing method of a MOS field-effect transistor in which such a structure is adopted that SiGe having a large lattice constant is embedded immediately below a channel and distortion is effectively introduced in a channel Si layer so that mobility ... | 11/29/2011 |
| 8043931 | Methods for forming multi-layer silicon structures The embodiments of the present invention are directed to the formation of multi-layer silicon structures by forming and attaching a plurality of individual layers or structures where each of the layers or the structures comprises at least silicon forming a desired p... | 10/25/2011 |
| 7943480 | Sub-lithographic dimensioned air gap formation and related structure Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over ... | 05/17/2011 |
| 7892940 | Device and methodology for reducing effective dielectric constant in semiconductor devices Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the... | 02/22/2011 |
| 7867870 | Semiconductor device and method for forming device isolation film of semiconductor device A device isolation film in a semiconductor device and a method for forming the same are provided. The method includes etching a middle portion of a device isolation film having a deposition structure including a Spin-On-Dielectric (SOD) oxide film and a High Density... | 01/11/2011 |
| 7863150 | Method to generate airgaps with a template first scheme and a self aligned blockout mask A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern. ... | 01/04/2011 |
| 7741191 | Method for preventing the formation of electrical shorts via contact ILD voids Densely spaced gates of field effect transistors usually lead to voids in a contact interlayer dielectric. If such a void is opened by a contact via and filled with conductive material, an electrical short between neighboring contact regions of neighboring transisto... | 06/22/2010 |
| 7687369 | Method of forming fine metal patterns for a semiconductor device using a damascene process A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardma... | 03/30/2010 |
| 7678661 | Method of forming an insulating layer in a semiconductor device Embodiments relate to semiconductor device and a method of forming an insulating layer with a low dielectric constant in a semiconductor device. The method may include forming a plurality of metal patterns on a semiconductor substrate, depositing a first insulating ... | 03/16/2010 |
| 7670924 | Air gap integration scheme Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure comprises depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and ... | 03/02/2010 |
| 7666753 | Metal capping process for BEOL interconnect with air gaps The embodiments of the invention provide a metal capping process for a BEOL interconnect with air gaps. More specifically an apparatus is provided comprising metal lines within a first dielectric. Metal caps are over the metal lines, wherein the metal caps contact t... | 02/23/2010 |
| 7629225 | Methods of manufacturing semiconductor devices and structures thereof Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insula... | 12/08/2009 |
| 7585743 | Manufacturing method for a semiconductor substrate comprising at least a buried cavity and devices formed with this method A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps: forming on the semiconductor substrate a pluralit... | 09/08/2009 |
| 7553739 | Integration control and reliability enhancement of interconnect air cavities An improved semiconductor device, integrated circuit, and integrated circuit fabrication method introduce highly controlled air cavities within high-speed copper interconnects. A polymer material is introduced on the edges of interconnect lines and vias within an in... | 06/30/2009 |
| 7534696 | Multilayer interconnect structure containing air gaps and method for making A multilevel air-gap-containing interconnect structure and a method of fabricating the same are provided. The multilevel air-gap-containing interconnect structure includes a collection of interspersed line levels and via levels, with via levels comprising conductive... | 05/19/2009 |
| 7531424 | Vacuum wafer-level packaging for SOI-MEMS devices A device and method for fabricating the device is disclosed. The device includes a substrate having an active layer disposed on a sacrificial layer. A trench is formed in the active layer to electrically isolate first and second regions in the active layer, and a no... | 05/12/2009 |
| 7524734 | Wiring substrate, electro-optic device, electric apparatus, method of manufacturing wiring substrate, method of manufacturing electro-optic device, and method of manufacturing electric apparatus A wiring substrate includes a substrate, a first film, and a second film formed between the substrate and the first film, and an empty space is formed between at least a part of the second film and the substrate. ... | 04/28/2009 |
| 7452784 | Formation of improved SOI substrates using bulk semiconductor wafers The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebe... | 11/18/2008 |
| 7439421 | Soybean variety XB22N06 According to the invention, there is provided a novel soybean variety designated XB22N06. This invention thus relates to the seeds of soybean variety XB22N06, to the plants of soybean XB22N06 to plant parts of soybean variety XB22N06 and to methods for producing a s... | 10/21/2008 |
| 7429504 | Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the p... | 09/30/2008 |
| 7429518 | Method for forming shallow trench isolation of semiconductor device A shallow trench isolation well is formed to be very thin in a highly integrated semiconductor device. When critical dimension (CD) is small, it is difficult to reduce the width of the photosensitive layer pattern for forming a trench to no more than a predetermined... | 09/30/2008 |
| 7396757 | Interconnect structure with dielectric air gaps An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a ... | 07/08/2008 |
| 7396732 | Formation of deep trench airgaps and related applications A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfille... | 07/08/2008 |
| 7396733 | Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device A method for manufacturing a semiconductor substrate, including: forming a first semiconductor layer on a semiconductive base; forming a second semiconductor layer, having a smaller etching selection ratio than that of the first semiconductor layer, on the first sem... | 07/08/2008 |
| 7391077 | Vertical type semiconductor device Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the first semiconductor layer and spaced apart from each other to form a t... | 06/24/2008 |
| 7374635 | Forming method and forming system for insulation film A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) ar... | 05/20/2008 |
| 7371653 | Metal interconnection structure of semiconductor device and method of forming the same Provided is a metal interconnection structure of a semiconductor device, having: a lower metal layer disposed on an insulating layer formed on a semiconductor device; a contact plug disposed on the lower metal layer; a supporting layer disposed to surround the conta... | 05/13/2008 |
| 7372086 | Semiconductor device including MOSFET and isolation region for isolating the MOSFET A semiconductor device comprises a semiconductor substrate, a MOSFET including a double gate structure provided on the semiconductor substrate, and an isolation region for isolating the MOSFET from other elements comprising a trench provided on the surface of the se... | 05/13/2008 |
| 7361991 | Closed air gap interconnect structure A closed air gap interconnect structure is described. The structure includes discrete regions of a permanent support dielectric under the interconnect lines so that the lines are substantially surrounded by air except for the discrete regions of the support dielectr... | 04/22/2008 |
| 7358148 | Adjustable self-aligned air gap dielectric for low capacitance wiring An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect adjacent a second interconnect on an interconnect level, spacers formed along adjacent sides of the first and second interconnects, and an air gap formed b... | 04/15/2008 |
| 7354834 | Semiconductor devices and methods to form trenches in semiconductor devices Semiconductor devices and methods of fabricating the same are disclosed. One example method may include forming sequentially a pad oxide film and a silicon nitride film on an entire surface of a semiconductor substrate, forming the trench by etching the silicon nitr... | 04/08/2008 |
| 7338888 | Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, ... | 03/04/2008 |
| 7335599 | Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layer... | 02/26/2008 |
| 7332406 | Air gap interconnect structure and method A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from th... | 02/19/2008 |
| 7329916 | DRAM cell arrangement with vertical MOS transistors The invention is related to a DRAM cell arrangement with vertical MOS transistors. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors bel... | 02/12/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7329602 | Wiring structure for integrated circuit with reduced intralevel capacitance A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated fr... | 02/12/2008 |
| 7319274 | Methods for selective integration of airgaps and devices made by such methods Methods for the production of airgaps in semiconductor devices and devices produced using such methods are disclosed. An example semiconductor device includes a damascene stack formed using such methods. The damascene stack includes a patterned dielectric layer incl... | 01/15/2008 |
| 7317253 | Cobalt tungsten phosphate used to fill voids arising in a copper metallization process A semiconductor device includes a substrate, at least one layer of functional devices formed on the substrate, a first dielectric layer formed over the functional device layer and a first trench/via located in the first dielectric layer. A copper conductor fills the... | 01/08/2008 |
