Class 438/420 - Plural doping steps

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making an junction isolated laterally spaced
No. of patents: 91
Last issue date: 04/29/2008

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Number	Title	Issue Date
7364997	Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et...	04/29/2008
7365388	Embedded trap direct tunnel non-volatile memory The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric consta...	04/29/2008
7338876	Method for manufacturing a semiconductor device A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor subs...	03/04/2008
7329583	Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does...	02/12/2008
7279378	Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does...	10/09/2007
7276431	Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does...	10/02/2007
7262110	Trench isolation structure and method of formation In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a ...	08/28/2007
7247544	High Q inductor integration In an inductor integration process, a high Q inductor is achieved by forming an AlCu inductor via prior to depositing the inductor dielectric. ...	07/24/2007
7229745	Lithographic semiconductor manufacturing using a multi-layered process Multilayer resist systems and techniques used for liftoff or planarizing topography wherein the dimensions and thicknesses of the layers are independently controlled. The undercut may also be independently controlled for precision structures. ...	06/12/2007
7214592	Method and apparatus for forming a semiconductor substrate with a layer structure of activated dopants Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant ...	05/08/2007
7169697	Semiconductor device and manufacturing method of the same Disclosed is a semiconductor device, comprising a first wiring structure formed on a semiconductor substrate and including a first plug and a first wiring formed on the first plug, and a second wiring structure formed on the semiconductor substrate belonging to the ...	01/30/2007
7163869	Shallow trench isolation structure with converted liner layer A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised o...	01/16/2007
7122452	Method of manufacturing a semiconductor on a silicon on insulator (SOI) substrate using solid epitaxial regrowth (SPER) and semiconductor device made thereby A method of producing a semiconductor device on a silicon on insulator (SOI) substrate is disclosed. In one aspect, the method comprises providing a device with a monocrystalline semiconductor layer on an insulating layer; providing a mask on the semiconductor layer...	10/17/2006
7119023	Process integration of SOI FETs with active layer spacer A method of manufacturing a microelectronics device including providing a substrate having an active layer, a dielectric layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural...	10/10/2006
7118979	Method of manufacturing transistor having germanium implant region on the sidewalls of the polysilicon gate electrode The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, in...	10/10/2006
7105387	Semiconductor device and manufacturing method for the same A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which ...	09/12/2006
7018928	Plasma treatment method to reduce silicon erosion over HDI silicon regions A method for reducing the loss of silicon in a plasma assisted photoresist etching process including providing a silicon substrate including a polysilicon gate structure; masking a portion of the silicon substrate with photoresist to carry out an ion implantation pr...	03/28/2006
7011978	Methods of forming capacitor constructions comprising perovskite-type dielectric materials with different amount of crystallinity regions The invention includes a capacitor construction. A capacitor electrode has a perovskite-type dielectric material thereover. The perovskite-type dielectric material has an edge region proximate the electrode, and a portion further from the electrode than the edge reg...	03/14/2006
7005340	Method for manufacturing semiconductor device A method is provided for manufacturing a semiconductor device that can reduce the number of steps in manufacturing a triple-well that includes multiple ion implantation steps and heat treatment steps. The method comprises the steps of: (a) forming a first mask layer...	02/28/2006
6982193	Method of forming a super-junction semiconductor device In one embodiment, a transistor is formed to have alternating depletion and conduction regions that are formed by doping the depletion and conduction regions through an opening in a substrate of the transistor. ...	01/03/2006
6977204	Method for forming contact plug having double doping distribution in semiconductor device The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and suppressing diffusions of dopants implanted into the contact. The do...	12/20/2005
6946339	Method for creating a stepped structure on a substrate In a method for creating a stepped structure on a substrate, which at least includes a first portion with a first thickness and a second portion with a second thickness, at first a layer sequence of a first oxide layer, a first nitride layer, and a second oxide laye...	09/20/2005
6929994	Method for manufacturing semiconductor device that includes well formation A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages in a common substrate. The method includes: (a) introducing an impurity of a second conduc...	08/16/2005
6927145	Bitline hard mask spacer flow for memory cell scaling The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adj...	08/09/2005
6821824	Semiconductor device and method of manufacturing the same A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which ...	11/23/2004
6730569	Field effect transistor with improved isolation structures An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from th...	05/04/2004
6699771	Process for optimizing junctions formed by solid phase epitaxy A method of forming a semiconductor device includes forming at least one amorphous region within an at least partially formed semiconductor device. The method also includes implanting a halogen species in the amorphous region of the at least partially for...	03/02/2004
6696350	Method of fabricating memory device A method of fabricating a memory device. A plurality of isolation structures and a plurality of stacked gate structures are sequentially formed on a substrate. While defining the stacked gate structures, the isolation structures are over etched to form a ...	02/24/2004
6537893	Substrate isolated transistor A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposit...	03/25/2003
6444522	Method of manufacturing a flash memory device with an antidiffusion region between well regions There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a break down voltage between wells is reduced and an insulating characteristic between the wells is lowered due to degraded barrier characteristic betw...	09/03/2002
6440805	Method of forming a semiconductor device with isolation and well regions A semiconductor device and its method of fabrication are disclosed. The method includes forming a first well region in a semiconductor substrate. The semiconductor substrate includes a first doped region below the first well region. The first well region ...	08/27/2002
6406974	Method of forming triple N well utilizing phosphorus and boron ion implantations A method of forming a triple N well is described. A first pattern mask layer is formed on a substrate. A first ion implantation step is performed to form an annular longitudinal deep N well in the substrate. A second ion implantation step is performed to ...	06/18/2002
6362035	Channel stop ion implantation method for CMOS integrated circuits A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. T...	03/26/2002
6303463	Method for fabricating a flat-cell semiconductor memory device A resist pattern with openings provided at the regions where N+ diffusion layers will be eventually formed is formed on a silicon substrate and thereafter, an N-type impurity is ion-doped to form N+ diffusion layers. Thereafter, gate...	10/16/2001
6255190	Method for dielectrically isolated deep pn-junctions in silicon substrates using deep trench sidewall predeposition technology A method for forming very deep pn-junctions without using epitaxy or extensively high temperature processing is provided. At least two parallel deep trenches are etched into a silicon substrate. Then the sidewalls of these trenches are predeposited by dopants....	07/03/2001
6169001	CMOS device with deep current path for ESD protection In this invention a current block is implanted into the drain of a transistor to provide for ESD protection and allow the shrinking of the transistor. The block increases the current path into the semiconductor bulk and increases heat dissipation capabili...	01/02/2001
6165868	Monolithic device isolation by buried conducting walls Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on trans...	12/26/2000
6063687	Formation of trench isolation for active areas and first level conductors A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path exten...	05/16/2000
6057184	Semiconductor device fabrication method using connecting implants A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecti...	05/02/2000
6033946	Method for fabricating an isolated NMOS transistor on a digital BiCMOS process A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N- conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type bur...	03/07/2000

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Class 438/420 - Plural doping steps