Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7326995 | Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. T... | 02/05/2008 |
| 7291884 | Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the t... | 11/06/2007 |
| 7279773 | Protection device for handling energy transients A protection device for handling energy transients includes a plurality of basic unit Zener diodes connected in series to achieve a desired breakdown voltage. Each of the basic unit Zener diodes is formed in a first-type substrate. Each of the basic unit Zener diode... | 10/09/2007 |
| 7132715 | Semiconductor device having a spacer layer doped with slower diffusing atoms than substrate A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient o... | 11/07/2006 |
| 7115523 | Method and apparatus for etching photomasks A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the ... | 10/03/2006 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 06/20/2006 |
| 7052966 | Deep N wells in triple well structures and method for fabricating same A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the ... | 05/30/2006 |
| 7049199 | Method of ion implantation for achieving desired dopant concentration A method for forming a plurality of MOSFETs wherein each one of the MOSFET has a unique predetermined threshold voltage. A doped well or tub is formed for each MOSFET. A patterned mask is then used to form a material line proximate each semiconductor well, wherein t... | 05/23/2006 |
| 7008836 | Method to provide a triple well in an epitaxially based CMOS or BiCMOS process A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition. ... | 03/07/2006 |
| 6998920 | Monolithically fabricated HBT amplification stage with current limiting FET A monolithically integrated amplifier comprising at least one heterojunction bipolar transistor and at least one field effect transistor is disclosed wherein the field effect transistor provides improved ruggedness by limiting the base and/or collector current to th... | 02/14/2006 |
| 6946339 | Method for creating a stepped structure on a substrate In a method for creating a stepped structure on a substrate, which at least includes a first portion with a first thickness and a second portion with a second thickness, at first a layer sequence of a first oxide layer, a first nitride layer, and a second oxide laye... | 09/20/2005 |
| 6900109 | Method of manufacturing a semiconductor device with a vertical drain drift layer of the alternating-conductivity-type A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a high breakdown voltage and to provide a method of manufacturing the s... | 05/31/2005 |
| 6828206 | Semiconductor device and method for fabricating the same In a method for fabricating a semiconductor device, a silicide material is formed at least on the surface of an area to be silicided. Then, a first RTA (Rapid Thermal Annealing) process is performed to form a first-reacted silicide region. Next, a supplemental silic... | 12/07/2004 |
| RE38510 | Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip The device uses the horizontal insulating region and the buried layer as the power transistor base and emitter respectively. An epitaxial growth is interposed between the two diffusions needed to form the aforesaid regions and those needed to create the base and the... | 05/04/2004 |
| 6677194 | Method of manufacturing a semiconductor integrated circuit device A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step... | 01/13/2004 |
| 6649498 | Metal film protection of the surface of a structure formed on a semiconductor substrate during etching of the substrate by a KOH etchant The present invention concerns the field of microstructures and in particular microstructures made via CMOS technology on semiconductor substrates intended to undergo micro-machining by wet chemical etching, in particular by a KOH etchant. According to th... | 11/18/2003 |
| 6645855 | Method for fabricating an integrated semiconductor product A method fabricates an integrated semiconductor product. The first step is providing a semiconductor wafer that has preformed semiconductor components. The next step is forming at least one connection, in particular a polysilicon connection. The next step... | 11/11/2003 |
| 6617217 | Reduction in well implant channeling and resulting latchup characteristics in shallow trench isolation by implanting wells through nitride Retrograde wells are formed by implanting through nitride films (40). Nitride films (40) are formed after STI (20) formation. By selectively masking a portion of the wafer with photoresist (47) after portions of a retrograde well are formed (45, 50, 55, a... | 09/09/2003 |
| 6586296 | Method of doping wells, channels, and gates of dual gate CMOS technology with reduced number of masks A method is provided for processing a semiconductor topography. In particular, a method is provided for forming wells of opposite conductivity type using a single patterned layer. In addition, the method may include forming a silicon layer having first an... | 07/01/2003 |
| 6538328 | Metal film protection of the surface of a structure formed on a semiconductor substrate during etching of the substrate by a KOH etchant The present invention concerns the field of microstructures and in particular microstructures made via CMOS technology on semiconductor substrates intended to undergo micro-machining by wet chemical etching, in particular by a KOH etchant. According to th... | 03/25/2003 |
| 6236100 | Semiconductor with high-voltage components and low-voltage components on a shared die A method and apparatus for increasing a breakdown voltage of a semiconductor device. The semiconductor device is constructed on a semiconductor substrate including an isolation diffusion region around the semiconductor device, a substrate layer, an epi la... | 05/22/2001 |
| 6165868 | Monolithic device isolation by buried conducting walls Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on trans... | 12/26/2000 |
| 6069048 | Reduction of silicon defect induced failures as a result of implants in CMOS and other integrated circuits A technique for reducing silicon defect induced transistor failures, such as latch-up, in a CMOS or other integrated circuit structure includes fabricating the integrated circuit structure on a substrate and implanting a buried layer beneath a surface of ... | 05/30/2000 |
| 6051457 | Method for fabricating electrostatic discharge protection device An integrated circuit with a passive component and an ESD device in accordance with the present invention has: a P substrate; an N+ buried layer implanted in the P substrate; a cathode coupled to the N+ buried layer with an N area formed between the catho... | 04/18/2000 |
| 5976923 | Method for fabricating a high-voltage semiconductor device A method for fabricating high-voltage semiconductor devices is disclosed, in which a P-well and a N-well are first formed over the substrate, where a plurality of P-wells and N-wells used as isolation regions and drift regions are further formed therein. ... | 11/02/1999 |
| 5976940 | Method of making plurality of bipolar transistors In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substr... | 11/02/1999 |
| 5938839 | Method for forming a semiconductor device A method for forming a semiconductor device is disclosed. The method comprises the step of irradiating a laser light to a surface of a semiconductor through a mask provided on said surface in an atmosphere comprising an impurity of one conductivity type t... | 08/17/1999 |
| 5633180 | Method of forming P-type islands over P-type buried layer A method of fabricating a vertical conductive region in a semiconductor device in which plural epitaxial layers are successively grown on a substrate and a dopant is implanted into each epitaxial layer before growing the next layer. A fast vertical transi... | 05/27/1997 |
| 5624858 | Method of manufacturing a semiconductor device with increased breakdown voltage A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration im... | 04/29/1997 |
| 5597742 | Semiconductor device and method The base region of the power stage and the horizontal isolation region of the integrated control circuit or collector region of a transistor of an integrated circuit consist of portions of an epitaxial layer with a first conductivity type grown in sequenc... | 01/28/1997 |
| 5591662 | Method of manufacturing a power integrated circuit (PIC) structure A PIC structure comprises a lightly doped semiconductor layer of a first conductivity type, superimposed over a heavily doped semiconductor substrate of the first conductivity type, wherein a power stage and a driving and control circuitry including first... | 01/07/1997 |
| 5556796 | Self-alignment technique for forming junction isolation and wells A method in accordance with one embodiment of the present invention may be used to self-align isolation regions, sinkers, and wells. In this improved method, P+ isolation regions, N+ sinkers, and P-wells are defined using the same masking step used to def... | 09/17/1996 |
| 5529939 | Method of making an integrated circuit with complementary isolated bipolar transistors Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor... | 06/25/1996 |
| 5470766 | Efficient method for fabricating optimal BiCMOS N-wells for bipolar and field effect transistors A BiCMOS process is provided for fabricating on the same semiconductor substrate three types of N-wells optimized respectively for (i) PMOS FETs requiring low P+/N-well capacitance; (ii) NPN bipolar transistors which do not require low collector-to-substr... | 11/28/1995 |
| 5451269 | Semiconductor memory device including an improved substrate structure and method of fabricating the same The invention provides a semiconductor substrate structure for semiconductor integrated circuit devices including a memory cell array area involving both stacked capacitors and transistors and a peripheral circuit area involving transistors. A portion of ... | 09/19/1995 |
| 5416039 | Method of making BiCDMOS structures A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired com... | 05/16/1995 |
| 5394007 | Isolated well and method of making A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type b... | 02/28/1995 |
| 5374582 | Laminated substrate for semiconductor device and manufacturing method thereof A method for fabricating a laminated substrate for a semiconductor device having a high voltage power device and a low voltage element formed in a region isolated from the power device with a P-N junction. The region for the low voltage element is formed ... | 12/20/1994 |
| 5330922 | Semiconductor process for manufacturing semiconductor devices with increased operating voltages A method of manufacturing semiconductor devices with increased operating voltages is described. A dopant of a second conductivity type is implanted into a region of a first epitaxial layer of the first conductivity type to form a buried layer. A substanti... | 07/19/1994 |
| 5273912 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device including forming an epitaxial layer on a second conductive silicon substrate selectively provided with a first conductive impurity diffusion layer and diffusing a second impurity through surface of the ep... | 12/28/1993 |
