Class 438/418 - Dopant addition

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making junction isolated laterally spaced semiconductor
No. of patents: 43
Last issue date: 02/09/2010

«First «Previous1 2 Next»Last»

Number	Title	Issue Date
7659179	Method of forming transistor using step STI profile in memory device A method of forming a memory device includes forming first and second isolation structures on a semiconductor substrate, the first and second isolation structures defining an active region therebetween; and etching a portion of the semiconductor substrate provided w...	02/09/2010
7524733	Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the acti...	04/28/2009
7304354	Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol...	12/04/2007
7262110	Trench isolation structure and method of formation In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a ...	08/28/2007
7141478	Multi-stage EPI process for forming semiconductor devices, and resulting device The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting ...	11/28/2006
6979627	Isolation trench A process for forming an isolation trench in a wafer. The process includes depositing (e.g. by a directional deposition process) a first dielectric material in the trench and then depositing a second dielectric material (e.g. by a directional deposition process) ove...	12/27/2005
6798015	Semiconductor device and method of manufacturing the same A semiconductor device according to the present invention includes a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each of the nonvolatile memory devices includes a word g...	09/28/2004
6737324	Method for fabricating raised source/drain of semiconductor device A method for fabricating a raised source/drain of a semiconductor device is described. A gate structure is formed on a substrate, and then a source/drain with a shallow-junction is formed in the substrate beside the gate structure. A spacer is formed on the sidewall...	05/18/2004
6703292	Method of making a semiconductor wafer having a depletable multiple-region semiconductor material Semiconductor devices are known comprising a multiple p-n junction RESURF semiconductor material (10) that provides a voltage-sustaining space-charge zone when depleted from a blocking junction (40). Charge balance is important in the alternating p-type (...	03/09/2004
6693018	Method for fabricating DRAM cell transistor having trench isolation structure The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion o...	02/17/2004
6649481	Methods of fabricating a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned mann...	11/18/2003
6607972	Method for producing an edge termination suitable for high voltages in a basic material wafer prefabricated according to the principle of lateral charge compensation An edge termination is produced that is capable of handling high voltages. The edge termination is produced in a base material wafer that is produced in accordance with the principle of lateral charge compensation. The edge termination is formed in the ba...	08/19/2003
6521508	Method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon process There is disclosed a method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon (SEG) process. The method includes forming a nitride film at a predetermined in a semiconductor substrate region except for t...	02/18/2003
6518124	Method of fabricating semiconductor device A method of fabricating a semiconductor device including the following steps of: forming a first insulating layer, a first conductive layer and a stopper layer over a semiconductor layer; forming a mask insulating layer on the first conductive layer in a ...	02/11/2003
6406973	Transistor in a semiconductor device and method of manufacturing the same The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective ...	06/18/2002
6319793	Circuit isolation utilizing MeV implantation A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected curren...	11/20/2001
6313000	Process for formation of vertically isolated bipolar transistor device A vertically-isolated bipolar transistor occupying reduced surface area is fabricated by circumscribing an expected active device region within a first narrow trench. The first trench is filled with sacrificial material impermeable to diffusion of conduct...	11/06/2001
6306728	Stable high voltage semiconductor device structure A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exis...	10/23/2001
6303463	Method for fabricating a flat-cell semiconductor memory device A resist pattern with openings provided at the regions where N+ diffusion layers will be eventually formed is formed on a silicon substrate and thereafter, an N-type impurity is ion-doped to form N+ diffusion layers. Thereafter, gate...	10/16/2001
6291309	Semiconductor device and method for manufacturing the same A semiconductor device which is mounted with a plurality of semiconductor chips. The fraction defective is low when the device is manufactured, and the efficiency of inspection is high. A method for manufacturing such a semiconductor device is also disclo...	09/18/2001
6274456	Monolithic device isolation by buried conducting walls Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on trans...	08/14/2001
6165868	Monolithic device isolation by buried conducting walls Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on trans...	12/26/2000
5938839	Method for forming a semiconductor device A method for forming a semiconductor device is disclosed. The method comprises the step of irradiating a laser light to a surface of a semiconductor through a mask provided on said surface in an atmosphere comprising an impurity of one conductivity type t...	08/17/1999
5849629	Method of forming a low stress polycide conductors on a semiconductor chip A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer on the surface of a substrate, forming a second un...	12/15/1998
5702973	Method for forming epitaxial semiconductor wafer for CMOS integrated circuits The present invention is a CMOS epitaxial semiconductor wafer (50) on which CMOS integrated circuits (16) can be manufactured, including such circuits that include bipolar components (referred to as "BiCMOS" circuits). The CMOS wafer includes a lightly do...	12/30/1997
5508210	Element isolating method for compound semiconductor device A method of element isolation includes implanting ions in a compound semiconductor substrate at the periphery of a semiconductor device in the substrate to produce a first insulating region having a region of maximum implanted ion concentration within a b...	04/16/1996
5451269	Semiconductor memory device including an improved substrate structure and method of fabricating the same The invention provides a semiconductor substrate structure for semiconductor integrated circuit devices including a memory cell array area involving both stacked capacitors and transistors and a peripheral circuit area involving transistors. A portion of ...	09/19/1995
5334546	Method of forming a semiconductor device which prevents field concentration There is provided p diffusion regions (18a, 18b) in the surface of an end portion of the n island (7) formed on the p- substrate (12). The insulation film (14) is formed on the n island (7) to form therein conductive plates (16a-16e). The p dif...	08/02/1994
5192712	Control and moderation of aluminum in silicon using germanium and germanium with boron A process is disclosed for controlling the diffusion of aluminum in silicon for the fabrication of monolithic pn junction isolated integrated circuits. Germanium is incorporated into the silicon where isolation or p-well diffusion of aluminum is to occur....	03/09/1993
5089428	Method for forming a germanium layer and a heterojunction bipolar transistor A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers...	02/18/1992
5070031	Complementary semiconductor region fabrication A method of forming oppositely doped semiconductor regions includes providing a first semiconductor layer of a first conductivity type and forming a second semiconductor layer of a second conductivity type on a portion of the first layer. A third semicond...	12/03/1991
4662061	Method for fabricating a CMOS well structure A process is disclosed for fabricating N-wells in a P-type substrate. An N-type epitaxial layer is formed on the surface of a P+ substrate. The N-type epitaxial layer is then masked and a doubly charged boron implant is performed on the exposed areas of t...	05/05/1987
4571275	Method for minimizing autodoping during epitaxial deposition utilizing a graded pattern subcollector The method suggests the replacement of all or part of the solid or blanket buried region, typically a subcollector region of a bipolar transistor, by a mesh or stripe shaped subcollector. During subsequent thermal processing involving growth of the epitax...	02/18/1986
4512816	High-density IC isolation technique capacitors A semiconductor substrate having an epitaxial layer on its upper surface is provided with a masking layer. Holes are photolithographically etched in the masking layer where isolation diffusion regions are to be formed. Then aluminum ions are implanted int...	04/23/1985
4381957	Method of diffusing aluminum A method of manufacturing a semiconductor device in which an aluminum-containing layer, hereinafter referred to as the aluminum source, is locally provided on a semiconductor body 1,2 of silicon and, in a subsequent diffusion treatment, aluminum is diffus...	05/03/1983
4346513	Method of fabricating semiconductor integrated circuit device utilizing selective etching and epitaxial refill A method of fabricating a semiconductor integrated circuit device wherein a substrate having a particular crystallographic orientation is selectively etched so as to form surface depressions of different depths. An epitaxial layer is grown from a Si--H--C...	08/31/1982
4281448	Method of fabricating a diode bridge rectifier in monolithic integrated circuit structure utilizing isolation diffusions and metal semiconductor rectifying barrier diode formation Method of fabricating monolithic integrated circuit structure incorporating a full-wave diode bridge rectifier of four Schottky diodes. A body of silicon is produced by growing an epitaxial layer of N-type silicon on a P-type substrate. P-type imparting m...	08/04/1981
4278987	Junction isolated IC with thick EPI portion having sides at least 20 degrees from (110) orientations A semiconductor device prepared by forming a silicon substrate of one conductor type having a surface of the (100) crystal plane, opening a rectangular window having sides parallel to the crystal axis, etching the interior of the rectangular window ...	07/14/1981
4276099	Fabrication of infra-red charge coupled devices In a method of fabricating semiconductor devices, eg infra-red charge coupled devices (IRCCDs), the invention relates to the provision of a region containing a first species of ionized dopant with a body of semiconductor material in which the device is be...	06/30/1981
4161417	Method of making CMOS structure with retarded electric field for minimum latch-up Method for making CMOS device utilizing a retarded electric field for reducing the current gain in the base region of parasitic transistors in the device. A buried layer is utilized in the base region of the parasitic transistor, and the resistivities of ...	07/17/1979

«First «Previous1 2 Next»Last»

PatentStorm

Did You Know...

PatentStorm News

Class 438/418 - Dopant addition