Class 438/414 - Isolation by PN junction only

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process whereby the laterally spaced regions of the semiconductor
No. of patents: 53
Last issue date: 10/25/2011

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Number	Title	Issue Date
8043930	Semiconductor memory device and method of manufacturing the same A semiconductor memory device includes first and second element isolation insulating films, first and second gate insulating films, first and second gate wiring and first and second mask layer. First and second upper surfaces of the first and second element isolatio...	10/25/2011
7674683	Bulk-isolated PN diode and method of forming a bulk-isolated PN diode A technique for making a bulk isolated PN diode is disclosed. In one embodiment, a method may include providing a substrate having a doped region and disposing a dielectric material over the doped region. The method may also include forming first and second holes in...	03/09/2010
7422938	Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does...	09/09/2008
7368364	Method for manufacturing element isolation structural section A plurality of element forming regions and an element isolation structural section forming region which separates the plurality of element forming regions from one another, are set to a substrate. A first thermal oxide film is formed. An HfSiON film is formed. Heati...	05/06/2008
7323394	Method of producing element separation structure A method of producing an element separation structure includes the steps of: forming a first thermal oxide film on the substrate; forming a silicon nitride film on the first thermal oxide film; removing the first thermal oxide film and the silicon nitride film in an...	01/29/2008
7256462	Semiconductor device The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region....	08/14/2007
7250323	Methods of making energy conversion devices with a substantially contiguous depletion regions A method of making an energy conversion device includes forming a plurality of pores within a substrate and forming a junction region within each of the plurality of pores. Each of the junction regions has a depletion region and each of the plurality of pores define...	07/31/2007
7161198	Semiconductor integrated circuit device having MOS transistor An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a par...	01/09/2007
7141484	Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation la...	11/28/2006
7132323	CMOS well structure and method of forming the same A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first ...	11/07/2006
7129519	Monitoring system comprising infrared thermopile detector The present invention relates to a semiconductor processing system that employs infrared-based thermopile detector for process control, by analyzing a material of interest, based on absorption of infrared light at a characteristic wavelength by such material. Specif...	10/31/2006
7049209	De-fluorination of wafer surface and related structure Methods of de-fluorinating a wafer surface after damascene processing and prior to photoresist removal are disclosed, as is a related structure. In one embodiment, the method places the wafer surface in a chamber and exposes the wafer surface to a plasma from a sour...	05/23/2006
6780685	Semiconductor device and manufacturing method thereof A semiconductor device has a semiconductor substrate of a first conductivity; and a first electrode formation region and a second electrode formation region formed adjacent to an inner surface of the semiconductor substrate. The first electrode formation regions and...	08/24/2004
6607972	Method for producing an edge termination suitable for high voltages in a basic material wafer prefabricated according to the principle of lateral charge compensation An edge termination is produced that is capable of handling high voltages. The edge termination is produced in a base material wafer that is produced in accordance with the principle of lateral charge compensation. The edge termination is formed in the ba...	08/19/2003
6589834	Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated f...	07/08/2003
6576944	Self-aligned nitride pattern for improved process window A device and method for fabricating a gate structure are disclosed. A first conductive material is deposited in a trench formed in a substrate and the first conductive material is recessed to a level below a top surface of the substrate in the trench. A d...	06/10/2003
6537893	Substrate isolated transistor A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposit...	03/25/2003
6531373	Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements The invention relates to a phase-change memory device that uses SOI in a chalcogenide volume of memory material. Parasitic capacitance, both vertical and lateral, are reduced or eliminated in the inventive structure....	03/11/2003
6436788	Field emission display having reduced optical sensitivity and method An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on a...	08/20/2002
6423604	Determination of thermal resistance for field effect transistor formed in SOI technology The thermal resistance Rth parameter is determined for a field effect transistor formed with a semiconductor film on a buried insulating material in SOI (semiconductor on insulator) technology. A p-n junction is formed with one of a drain regio...	07/23/2002
6383855	High speed, low cost BICMOS process using profile engineering A bipolar complementary metal oxide semiconductor device has a c-well fabricated using profile engineering (a multi-energy implant using accurate dosages and energies determined by advance simulation) to provide a higher c-well implant dose while creating...	05/07/2002
6372607	Photodiode structure A circuit that includes an isolation boundary formed to a depth in a substrate defining an active area of the substrate, a primary junction formed in the active area to a primary junction depth in the substrate to collect electron/hole pairs, and a second...	04/16/2002
6365468	Method for forming doped p-type gate with anti-reflection layer A method for forming doped p-type gate is disclosed as the following description. The method includes that, firstly, a semiconductor substrate is provided. The semiconductor substrate is etched to form a concave portion as a shallow trench isolation. A fi...	04/02/2002
6303983	Apparatus for manufacturing resin-encapsulated semiconductor devices A semiconductor device includes a lead frame, a semiconductor chip, a resin-encapsulated portion, and tie bars. The semiconductor chip is mounted on a die pad of the lead frame. The resin-encapsulated portion resin-encapsulates the semiconductor chip. The...	10/16/2001
6303463	Method for fabricating a flat-cell semiconductor memory device A resist pattern with openings provided at the regions where N+ diffusion layers will be eventually formed is formed on a silicon substrate and thereafter, an N-type impurity is ion-doped to form N+ diffusion layers. Thereafter, gate...	10/16/2001
6228704	Process for manufacturing semiconductor integrated circuit device To provide a process for manufacturing a semiconductor integrated circuit device in which ion implantation of an embedded diffused layer for forming triple-well and oxide film etching for forming two types of gate oxide films having different thicknesses ...	05/08/2001
6165822	Silicon carbide semiconductor device and method of manufacturing the same A vertical type power MOSFET made of silicon carbide includes a surface channel layer doped with nitrogen as dopant with a concentration equal to or less than 1×1015 cm-3. Accordingly, when a gate oxide film is formed on the surface...	12/26/2000
6165868	Monolithic device isolation by buried conducting walls Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on trans...	12/26/2000
6130139	Method of manufacturing trench-isolated semiconductor device The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portio...	10/10/2000
6093620	Method of fabricating integrated circuits with oxidized isolation A thin silicon epitaxial layer, formed on a silicon substrate, is subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction....	07/25/2000
6004861	Process for making a discontinuous source/drain formation for a high density integrated circuit A semiconductor process including forming a gate dielectric on a semiconductor substrate. First and second conductive gates are then formed on the gate dielectric. The conductive gates are aligned over respective channel regions of the substrate. The chan...	12/21/1999
6001704	Method of fabricating a shallow trench isolation by using oxide/oxynitride layers A stacked layer including a first oxide, a nitride layer, a second oxide layer and an oxynitride layer is formed on the top of the first oxide layer. An etching is performed through a photoresist to etch the oxynitride, the second oxide and nitride. Oxide...	12/14/1999
5950076	Methods of forming silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buri...	09/07/1999
5942783	Semiconductor device having improved latch-up protection A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semicondu...	08/24/1999
5880001	Method for forming epitaxial pinched resistor having reduced conductive cross sectional area An epitaxial pinched resistor includes a semiconductor substrate of a first conductivity type having a surface on which an epitaxial layer of a second conductivity type grown. An up isolation region of the first conductivity type is diffused from the surf...	03/09/1999
5856218	Bipolar transistor formed by a high energy ion implantation method In an NPN bipolar transistor having a special structure in which each impurity region is formed by ion implantation, a width of a base region is significantly reduced, and therefore, current amplification factor hfe is increased, resulting in improvement ...	01/05/1999
5789288	Process for the fabrication of semiconductor devices having various buried regions A process for doping a P-type substrate (50) by forming a layer (52) of silicon nitride, implanting N-type impurities through this layer (FIG. 7), forming a resist mask (54) which leaves at least one area of the substrate (FIG. 8) containing a part of the...	08/04/1998
5776807	Method for fabricating a triple well for bicmos devices To accomplish the above objectives, the present invention provides a method of fabricating a collector well in a semiconductor BiCMOS device. The method begins by providing a substrate having c-well areas, N-well areas, and P-well areas. The substrate has...	07/07/1998
5696004	Method of producing semiconductor device with a buried layer A method of producing a semiconductor device having a high concentration N-type buried layer on a P-type silicon substrate, the buried layer being covered with a P-type silicon epitaxial layer. The method comprises forming a P-type high concentration laye...	12/09/1997
5334546	Method of forming a semiconductor device which prevents field concentration There is provided p diffusion regions (18a, 18b) in the surface of an end portion of the n island (7) formed on the p- substrate (12). The insulation film (14) is formed on the n island (7) to form therein conductive plates (16a-16e). The p dif...	08/02/1994

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Class 438/414 - Isolation by PN junction only