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| Number | Title | Issue Date |
| 8119494 | Defect-free hetero-epitaxy of lattice mismatched semiconductors A method includes providing a semiconductor substrate formed of a first semiconductor material; and forming a plurality of insulation regions over at least a portion of the semiconductor substrate, with a plurality of trenches separating the plurality of insulation ... | 02/21/2012 |
| 7989306 | Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternatin... | 08/02/2011 |
| 7951684 | Semiconductor device method of manfacturing a quantum well structure and a semiconductor device comprising such a quantum well structure A semiconductor device (1) and a method are disclosed for obtaining on a substrate (2) a multilayer structure (3) with a quantum well structure (4). The quantum well structure (4) comprises a semiconductor layer (5) sandwich... | 05/31/2011 |
| 7927962 | Semiconductor device having buried insulation films and method of manufacturing the same A method of manufacturing a semiconductor device and a semiconductor device manufactured by the method, the method comprising: (a) forming a buffer layer on a semiconductor substrate; (b) patterning the buffer layer in a first direction to form buffer layer patterns... | 04/19/2011 |
| 7838388 | Method for producing SOI substrate Provided is a method for producing an SOI substrate having a thick-film SOI layer, in which an ion-implanted layer is formed by implanting at least one kind of ion of hydrogen ion and a rare gas ion into a surface of a bond wafer, an SOI substrate having an SOI laye... | 11/23/2010 |
| 7803690 | Epitaxy silicon on insulator (ESOI) Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI s... | 09/28/2010 |
| 7759213 | Pattern independent Si:C selective epitaxy Trenches are formed in a silicon substrate by etching exposed portions of the silicon substrate. After covering areas on which deposition of Si:C containing material is to be prevented, selective epitaxy is performed in a single wafer chamber at a temperature from a... | 07/20/2010 |
| 7691720 | Vertical nanotube semiconductor device structures and methods of forming the same Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric m... | 04/06/2010 |
| 7670923 | Method of fabricating strain-silicon CMOS Recesses are formed in the drain and source regions of an MOS transistor. The recesses are formed using two anisotropic etch processes and first and second sidewall spacers. The recesses are made up of first and second recesses, and the depths of the first and secon... | 03/02/2010 |
| 7405098 | Smooth surface liquid phase epitaxial germanium A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the si... | 07/29/2008 |
| 7390710 | Protection of tunnel dielectric using epitaxial silicon Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon... | 06/24/2008 |
| 7364990 | Epitaxial crystal growth process in the manufacturing of a semiconductor device First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown,... | 04/29/2008 |
| 7329923 | High-performance CMOS devices on hybrid crystal oriented substrates An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is... | 02/12/2008 |
| 7320926 | Shallow trench filled with two or more dielectrics for isolation and coupling for stress control A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and fi... | 01/22/2008 |
| 7303963 | Method for manufacturing cell transistor Disclosed herein is a method of manufacturing a cell transistor which can achieve an improvement in a short-channel effect of a cell transistor as well as an improvement in a refresh characteristic of the transistor, and can also prevent a reduction in the threshold... | 12/04/2007 |
| 7271023 | Floating body germanium phototransistor A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the i... | 09/18/2007 |
| 7271066 | Semiconductor device and a method of manufacturing the same Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate... | 09/18/2007 |
| 7235433 | Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the ... | 06/26/2007 |
| 7202143 | Low temperature production of large-grain polycrystalline semiconductors An oxide or nitride layer is provided on an amorphous semiconductor layer prior to performing metal-induced crystallization of the semiconductor layer. The oxide or nitride layer facilitates conversion of the amorphous material into large grain polycrystalline mater... | 04/10/2007 |
| 7199031 | Semiconductor system having a pn transition and method for manufacturing a semiconductor system A semiconductor system having a pn transition and a method for manufacturing a semiconductor system are disclosed. The semiconductor system is designed in the form of a chip having an edge region, the semiconductor system includes a first layer of a first conductivi... | 04/03/2007 |
| 7195985 | CMOS transistor junction regions formed by a CVD etching and deposition sequence This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent dep... | 03/27/2007 |
| 7195984 | Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to re... | 03/27/2007 |
| 7183175 | Shallow trench isolation structure for strained Si on SiGe A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench... | 02/27/2007 |
| 7183573 | Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of ... | 02/27/2007 |
| 7176101 | Method of forming isolation oxide layer in semiconductor integrated circuit device A method is provided in which a first oxide layer is deposited on a silicon substrate and etched to form openings. A first silicon epitaxial layer is grown on the substrate in the openings, forming first active regions, a second oxide layer is deposited thereon, and... | 02/13/2007 |
| 7175966 | Water and aqueous base soluble antireflective coating/hardmask materials A multilayer lithographic structure which includes a substrate, having on a major surface thereof a first layer including a water and/or aqueous base soluble material which includes Ge, O, and H, and optionally X, wherein X is at least one of Si, N, and F; and dispo... | 02/13/2007 |
| 7172930 | Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semi... | 02/06/2007 |
| 7170184 | Treatment of a ground semiconductor die to improve adhesive bonding to a substrate Methods are provided to improve the adhesive bonding of a semiconductor die to a substrate through an adhesive paste by forming a layer of silicon dioxide on the back surface of the semiconductor die prior to applying the adhesive paste. Contacting the semiconductor... | 01/30/2007 |
| 7166520 | Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process A method for fabricating one or more devices, e.g., integrated circuits. The method includes providing a substrate (e.g., silicon), which has a thickness of semiconductor material and a surface region. The substrate also has a cleave plane provided within the substr... | 01/23/2007 |
| 7144764 | Method of manufacturing semiconductor device having trench isolation The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitri... | 12/05/2006 |
| 7132347 | Semiconductor device with trench structure and method for manufacturing the same A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define siz... | 11/07/2006 |
| 7118976 | Methods of manufacturing MOSFETs in semiconductor devices Methods of fabricating MOSFETs in semiconductor/r devices are disclosed. One example method may include forming an isolation layer on a semiconductor substrate and forming a capping layer thereon, forming an epitaxial active region which is not covered with the isol... | 10/10/2006 |
| 7105895 | Epitaxial SiObarrier/insulation layer A method for producing an insulating or barrier layer (FIG. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects... | 09/12/2006 |
| 7094634 | Structure and method for manufacturing planar SOI substrate with multiple orientations The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface co... | 08/22/2006 |
| 7081397 | Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant reg... | 07/25/2006 |
| 7071039 | Manufacturing method of partial SOI wafer, semiconductor device using the partial SOI wafer and manufacturing method thereof A semiconductor device includes a first semiconductor region having a buried oxide layer formed therein, a second semiconductor region in which the buried oxide layer does not exist, a trench formed to such a depth as to reach at least the buried oxide layer in a bo... | 07/04/2006 |
| 7067846 | Semiconductor light-emitting device, surface-emission laser diode, and production apparatus thereof, production method, optical module and optical telecommunication system A semiconductor light-emitting device has a semiconductor layer containing Al between a substrate and an active layer containing nitrogen, wherein Al and oxygen are removed from a growth chamber before growing said active layer and a concentration of oxygen incorpor... | 06/27/2006 |
| 7045435 | Shallow trench isolation method for a semiconductor wafer The present invention relates to a shallow trench isolation method of a semiconductor wafer which fills dielectric material into shallow trenches between components on the surface of the semiconductor wafer to electrically isolate the components. This method can pre... | 05/16/2006 |
| 7018904 | Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer l... | 03/28/2006 |
| 7018886 | Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and fi... | 03/28/2006 |
