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| Number | Title | Issue Date |
| 7687368 | Semiconductor device manufacturing method A semiconductor device manufacturing method is disclosed. The method is to form a second semiconductor layer which has less susceptibility to adopting insulative characteristics than a first semiconductor layer on the first semiconductor layer. Then, grooves which e... | 03/30/2010 |
| 7432173 | Methods of fabricating silicon-on-insulator substrates having a laser-formed single crystalline film In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor... | 10/07/2008 |
| 7422960 | Method of forming gate arrays on a partial SOI substrate The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. Th... | 09/09/2008 |
| 7381656 | Method of manufacturing a semiconductor device and semiconductor device obtained by means of said method The invention relates to a method of manufacturing a semiconductor device comprising a substrate (1) and a semiconductor body (2) in which at least one semiconductor element is formed, wherein, in the semiconductor body (2), a semiconductor isla... | 06/03/2008 |
| 7368340 | Semiconductor device and method of making semiconductor devices A semiconductor device includes a semiconductor substrate in which an insulating layer is formed in a part of an region, a semiconductor layer is formed by epitaxial growth and located on the insulating layer, a first gate electrode is formed at the sidewall of the ... | 05/06/2008 |
| 7361563 | Methods of fabricating a semiconductor device using a selective epitaxial growth technique Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are... | 04/22/2008 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre... | 04/08/2008 |
| 7351616 | Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate and method for manufacturing semiconductor device A semiconductor substrate comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; and semiconductor layers of mutually different film thicknesses formed on the dielectric layers. ... | 04/01/2008 |
| 7352025 | Semiconductor memory device with increased node capacitance An integrated circuit semiconductor memory device having the BOX layer removed from under the gate of a storage transistor to increase the gate-to-substrate capacitance and reduce the soft error rate. The increased node capacitance thus obtained is achieved without ... | 04/01/2008 |
| 7332775 | Protruding spacers for self-aligned contacts A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous c... | 02/19/2008 |
| 7320916 | Manufacturing method of semiconductor device When Ti as a barrier metal layer is brought into contact with a diffusion region of boron provided on a surface of a silicon substrate, there is a problem that boron is absorbed by titanium silicide, and contact resistance is increased. Although there is a method of... | 01/22/2008 |
| 7302856 | Strain sensors based on nanowire piezoresistor wires and arrays A highly sensitive and ultra-high density array of electromechanical nanowires is fabricated. Nanowires are extremely sensitive to the strain induced by the attachment of biological and chemical species. Real-time detection is realized through piezoresistive transdu... | 12/04/2007 |
| 7294201 | Method of manufacturing crystal of III-V compound of the nitride system, crystal substrate of III-V compound of the nitride system, crystal film of III-V compound of the nitride system, and method of manufacturing device A crystal substrate and a crystal film of a III-V compound of the nitride system which are manufactured easily and have few dislocations as well as a method of manufacturing a crystal and a method of manufacturing a device with the use thereof are disclosed. On a ba... | 11/13/2007 |
| 7288828 | Metal oxide semiconductor transistor device A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gat... | 10/30/2007 |
| 7288425 | Hybrid cantilever and tip A storage device having a read/write mechanism including a cantilever portion. The cantilever portion includes a non-single-crystal silicon body portion and a single crystal silicon tip. ... | 10/30/2007 |
| 7273788 | Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to... | 09/25/2007 |
| 7268397 | Thermal dissipation structures for finfets A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer include... | 09/11/2007 |
| 7262428 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 08/28/2007 |
| 7262109 | Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semicond... | 08/28/2007 |
| 7256077 | Method for removing a semiconductor layer A method of forming a semiconductor device includes forming a first layer over a semiconductor substrate and forming a second layer over the first layer. The second layer includes silicon and has an etch selectivity to the second layer that is greater than approxima... | 08/14/2007 |
| 7253034 | Dual SIMOX hybrid orientation technology (HOT) substrates This invention provides a separation by implanted oxygen (SIMOX) method for forming planar hybrid orientation semiconductor-on-insulator (SOI) substrates having different crystal orientations, thereby making it possible for devices to be fabricated on crystal orient... | 08/07/2007 |
| 7247534 | Silicon device on Si:C-OI and SGOI and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second mat... | 07/24/2007 |
| 7247908 | Method of fabricating a FinFET A FinFET structure and method of forming a FinFET device. The method includes: (a) providing a semiconductor substrate, (b) forming a dielectric layer on a top surface of the substrate; (c) forming a silicon fin on a top surface of the dielectric layer; (d) forming ... | 07/24/2007 |
| 7220654 | Method for manufacturing semiconductor substrate An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a s... | 05/22/2007 |
| 7221024 | Transistor having dielectric stressor elements for applying in-plane shear stress A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a dire... | 05/22/2007 |
| 7217606 | Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, soi and thin film structures A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS tran... | 05/15/2007 |
| 7205184 | Method of crystallizing silicon film and method of manufacturing thin film transistor liquid crystal display A method of crystallizing a silicon film by which it is possible to obtain a polycrystalline silicon thin film having a uniform crystal structure and a good quality, and a method of manufacturing a thin film transistor-liquid crystal display (TFT-LCD) using the same... | 04/17/2007 |
| 7199031 | Semiconductor system having a pn transition and method for manufacturing a semiconductor system A semiconductor system having a pn transition and a method for manufacturing a semiconductor system are disclosed. The semiconductor system is designed in the form of a chip having an edge region, the semiconductor system includes a first layer of a first conductivi... | 04/03/2007 |
| 7190029 | Preventive treatment method for a multilayer semiconductor wafer A preventive treatment method for a multilayer semiconductor wafer is described. The semiconductor wafer includes a supporting substrate, at least one intermediate layer and a surface layer in which an intermediate layer has an exposed lateral edge and the wafer is ... | 03/13/2007 |
| 7153753 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 12/26/2006 |
| 7141821 | Semiconductor device having an impurity gradient in the impurity regions and method of manufacture The active layer of an n-channel TFT is formed with a channel forming region, a first impurity region, a second impurity region and a third impurity region. In this case, the concentration of the impurities in each of the impurity regions is made higher as the regio... | 11/28/2006 |
| 7115480 | Micromechanical strained semiconductor by wafer bonding One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a first semiconductor wafer such that the surface of the first semiconductor wafer h... | 10/03/2006 |
| 7109072 | Semiconductor material, field effect transistor and manufacturing method thereof The silicon wires formed around metal particles by crystal growth have the problem of metal pollution. For its solution, in the present invention, a silicon bridge is formed through standard silicon processes such as the lithography and the wet etching using hydrofl... | 09/19/2006 |
| 7105866 | Heterojunction tunneling diodes and process for fabricating same High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the ... | 09/12/2006 |
| 7101772 | Means for forming SOI A method for forming a SOI structure in which porous silicon is sealed and an epitaxial layer is grown thereover, followed by implantation of oxygen and annealing. ... | 09/05/2006 |
| 7101444 | Defect-free semiconductor templates for epitaxial growth A semiconductor device includes at least one defect-free epitaxial layer. At least a part of the device is manufactured by a method of fabrication of defect-free epitaxial layers on top of a surface of a first solid state material having a first thermal evaporation ... | 09/05/2006 |
| 7087499 | Integrated antifuse structure for FINFET and CMOS devices A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a subst... | 08/08/2006 |
| 7084044 | Optoelectronic device and method of manufacture thereof The present invention provides an optoelectronic device and a method of manufacture thereof. In one embodiment, the method of manufacturing the optoelectronic device may include creating a multilayered optical substrate and then forming a self aligned dual mask over... | 08/01/2006 |
| 7078278 | Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same A dual-metal CMOS arrangement and method of making the same provides a substrate and a plurality of NMOS devices and PMOS devices formed on the substrate. Each of the plurality of NMOS devices and PMOS devices have gate electrodes. Each NMOS gate electrode includes ... | 07/18/2006 |
| 7067874 | Semiconductor device including trench with at least one of an edge of an opening and a bottom surface being round A semiconductor device that includes an insulating substrate, a plurality of semiconductor layers arranged to be isolated from one another on the insulating substrate, and a semiconductor element independently provided on the semiconductor layers. Further, a trench ... | 06/27/2006 |
