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| Number | Title | Issue Date |
| 8071459 | Method of sealing an air gap in a layer of a semiconductor structure and semiconductor structure A method of sealing an air gap in a layer of a semiconductor structure comprises providing a first layer of the semiconductor structure having at least one air gap for providing isolation between at least two conductive lines formed in the first layer. The at least ... | 12/06/2011 |
| 7923345 | Methods relating to trench-based support structures for semiconductor devices A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to ... | 04/12/2011 |
| 7871894 | Process for manufacturing thick suspended structures of semiconductor material A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front ... | 01/18/2011 |
| 7696060 | Recyclable stamp device and recyclable stamp process for wafer bond A recyclable stamp device and a recyclable stamp process for wafer bond are provided. The recyclable stamp device includes a substrate, a protective layer, a stack film structure and a cap. The protective layer is disposed on the substrate. An opening is positioned ... | 04/13/2010 |
| 7514335 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes providing a base plate; mounting a plurality of semiconductor chips, the plural semiconductor chips being mounted apart from each other; forming an insulating film on an upper surface of the base; forming a p... | 04/07/2009 |
| 7429504 | Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the p... | 09/30/2008 |
| 7396757 | Interconnect structure with dielectric air gaps An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a ... | 07/08/2008 |
| 7375032 | Semiconductor substrate thinning method for manufacturing thinned die In a method according to the present invention, a substrate thinning process is performed on a bumped substrate prior to the ultimate solder reflow process to heal bump defects caused by the substrate thinning process. Concurrently, the risk of substrate breakage is... | 05/20/2008 |
| 7371602 | Semiconductor package structure and method for manufacturing the same A semiconductor package structure comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surface; pad extension ... | 05/13/2008 |
| 7358179 | Method of manufacturing semiconductor device including air space formed around gate electrode After a HEMT is formed, side walls are formed on a semiconductor substrate. Next, a sacrificial layer is formed to cover the HEMT. Next, contact holes are formed in the sacrificial layer to expose upper surfaces of source electrodes. Next, a metal interconnect line ... | 04/15/2008 |
| 7351641 | Structure and method of forming capped chips As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern is formed on a chip insulated from wiring of the chip, and a cap is formed including a metal. The cap is joined to the metal ... | 04/01/2008 |
| 7335599 | Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layer... | 02/26/2008 |
| 7302982 | Label applicator and system A label applicator including a support surface having a central area and curving downwardly from the central area. A post assembly extends up from the central area such that a label having a label through-hole can be positioned in a support position generally on the... | 12/04/2007 |
| 7302848 | Force compensated comb drive A force compensated comb drive for a microelectromechanical system includes a MEMS mechanism for providing an output signal representative of a physical quantity; a comb drive for actuating the MEMS mechanism; a comb drive circuit for providing a drive signal to the... | 12/04/2007 |
| 7301207 | Semiconductor device capable of threshold voltage adjustment by applying an external voltage A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surfa... | 11/27/2007 |
| 7294934 | Low-K dielectric structure and method A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a suitable porous or low density permeable material. At an appropriate time, the underlying sacrificial material is decomposed and diffused away through the overlying p... | 11/13/2007 |
| 7285474 | Air-gap insulated interconnections Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, th... | 10/23/2007 |
| 7285434 | Semiconductor package and method for manufacturing the same A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on th... | 10/23/2007 |
| 7285433 | Integrated devices with optical and electrical isolation and method for making The invention is directed to a method for optical and electrical isolation between adjacent integrated devices. The method comprises the steps of forming at least one trench through an exposed surface of a semiconductor wafer by removing a portion of the semiconduct... | 10/23/2007 |
| 7279720 | Large bumps for optical flip chips The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer. ... | 10/09/2007 |
| 7268646 | Temperature controlled MEMS resonator and method for controlling resonator frequency There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a temperature compensated microelectromechanical resonator as well as fabricating, manufacturing, providing and/or controlling microelectromechanical reso... | 09/11/2007 |
| 7264995 | Method for manufacturing wafer level chip scale package using redistribution substrate The present invention provides a method for manufacturing a wafer level chip scale package using a redistribution substrate, which has patterned bump pairs connected by redistribution lines and formed on a transparent insulating substrate. The redistribution substra... | 09/04/2007 |
| 7256077 | Method for removing a semiconductor layer A method of forming a semiconductor device includes forming a first layer over a semiconductor substrate and forming a second layer over the first layer. The second layer includes silicon and has an etch selectivity to the second layer that is greater than approxima... | 08/14/2007 |
| 7253078 | Method and apparatus for forming an underfill adhesive layer An apparatus and method for forming a layer of underfill adhesive on an integrated circuit in wafer form is described. In one embodiment, the layer of underfill adhesive is disposed and partially cured on the active surface of the wafer. Once the underfill adhesive ... | 08/07/2007 |
| 7253082 | Pasted SOI substrate, process for producing the same and semiconductor device A plurality of recessed portions having different depths is formed in a surface of the active layer wafer or in a bonding surface of the supporting substrate wafer. Those wafers are bonded to each other with an insulation film interposed therebetween. This allows a ... | 08/07/2007 |
| 7247562 | Semiconductor element, semiconductor device and methods for manufacturing thereof The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield ... | 07/24/2007 |
| 7242012 | Lithography device for semiconductor circuit pattern generator General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 07/10/2007 |
| 7235456 | Method of making empty space in silicon To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate. ... | 06/26/2007 |
| 7229894 | Active cell isolation body of a semiconductor device and method for forming the same An active cell isolation body of a semiconductor device and a method for forming the same are disclosed. An example active cell isolation body of a semiconductor device includes a trench with a depth in a semiconductor substrate at an active cell isolation region, a... | 06/12/2007 |
| 7230314 | Semiconductor device and method of forming a semiconductor device A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provid... | 06/12/2007 |
| 7223696 | Methods for maskless lithography General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 05/29/2007 |
| 7217604 | Structure and method for thin box SOI device A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the devic... | 05/15/2007 |
| 7215009 | Expansion plane for PQFP/TQFP IR—package design Provided is a lead frame package with an expansion plane to minimize electrical parasitics introduced into the semiconductor chip's electrical system (e.g., power delivery system, signal loops, etc.). Also provided are methods for assembling such lead frame packages... | 05/08/2007 |
| 7214594 | Method of making semiconductor device using a novel interconnect cladding layer A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive in... | 05/08/2007 |
| 7211496 | Freestanding multiplayer IC wiring structure A dielectric wiring structure and method of manufacture therefor. The wiring structure includes air dielectric formed in a hemisphere. The wiring structure also includes, in embodiments, a method of simultaneously forming a MEMS structure with a transistor circuit u... | 05/01/2007 |
| 7205248 | Method of eliminating residual carbon from flowable oxide fill Methods of forming an oxide layer such as high aspect ratio trench isolations, and treating the oxide substrate to remove carbon, structures formed by the method, and devices and systems incorporating the oxide material are provided. ... | 04/17/2007 |
| 7202137 | Process for producing an integrated electronic circuit comprising superposed components and integrated electronic circuit thus obtained A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at... | 04/10/2007 |
| 7199056 | Low cost and low dishing slurry for polysilicon CMP Methods and compositions are provided for planarizing substrate surfaces with low dishing. Aspects of the invention provide methods of using compositions comprising an abrasive selected from the group consisting of alumina and ceria and a surfactant for chemical mec... | 04/03/2007 |
| 7192887 | Semiconductor device with nitrogen in oxide film on semiconductor substrate and method of manufacturing the same A method of manufacturing a MOS transistor is provided that achieves high-speed devices by reducing nitrogen diffusion to a silicon substrate interface due to redistribution of nitrogen and further suppressing its diffusion to a polysilicon interface, which prevents... | 03/20/2007 |
| 7193239 | Three dimensional structure integrated circuit A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, red... | 03/20/2007 |
