Celebrity Inventors
Walt Disney was no Mickey Mouse inventor. He devised a serious animation camera which he patented. With the device, his company created "Snow White".
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7820521 | Conductive through via structure and process for electronic device carriers Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form a... | 10/26/2010 |
| 7442618 | Method to engineer etch profiles in Si substrate for advanced semiconductor devices Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill t... | 10/28/2008 |
| 7381662 | Methods for improving the cracking resistance of low-k dielectric materials Methods for improving the mechanical properties of a CDO film are provided. The methods involve, for instance, providing either a dense CDO film or a porous CDO film in which the porogen has been removed followed by curing the CDO film at an elevated temperature usi... | 06/03/2008 |
| 7381862 | Identification of soybeans having resistance to The invention provides soybean plants having a novel determinant, Rps8, for resistance to Phytophthora sojae. The invention also provides methods for identifying germplasms that are either heterozygous or homozygous for Rps8 using marker assisted selection. G... | 06/03/2008 |
| 7316979 | Method and apparatus for providing an integrated active region on silicon-on-insulator devices A method and apparatus for providing integrated active regions on silicon-on-insulator (SOI) devices by oxidizing a portion of the active layer. When the active layer of the SOI wafer is relatively thick, such as about 200 Å to 1000 Å or greater, the etching pro... | 01/08/2008 |
| 7294536 | Process for manufacturing an SOI wafer by annealing and oxidation of buried channels A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.... | 11/13/2007 |
| 7288802 | Virtual body-contacted trigate A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and th... | 10/30/2007 |
| 7273788 | Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to... | 09/25/2007 |
| 7262428 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 08/28/2007 |
| 7227176 | Etch stop layer system A semiconductor structure including a uniform etch-stop layer. The uniform etch stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×1019 boron atoms/cm3. A method for forming a semicon... | 06/05/2007 |
| 7220656 | Strained semiconductor by wafer bonding with misorientation One aspect of the present invention relates to a method for forming a strained semiconductor structure. In various embodiments, at least two strong bonding regions are defined for a desired bond between a crystalline semiconductor membrane and a crystalline semicond... | 05/22/2007 |
| 7198974 | Micro-mechanically strained semiconductor film One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor film is formed on a substrate surface, and a recess is created beneath the film. A portion of the film is... | 04/03/2007 |
| 7195987 | Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-x... | 03/27/2007 |
| 7173274 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe bas... | 02/06/2007 |
| 7157770 | MOS transistor with recessed gate and method of fabricating the same A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trenc... | 01/02/2007 |
| 7153753 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 12/26/2006 |
| 7132349 | Methods of forming integrated circuits structures including epitaxial silicon layers in active regions An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active reg... | 11/07/2006 |
| 7132695 | Light emitting diode having a dual dopant contact layer A light emitting diode with a dual dopant contact layer. The light emitting diode includes a substrate, a light emitting stacked structure formed on the substrate, a dual dopant contact layer formed on the light emitting stacked structure, and a transparent conducti... | 11/07/2006 |
| 7115480 | Micromechanical strained semiconductor by wafer bonding One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a first semiconductor wafer such that the surface of the first semiconductor wafer h... | 10/03/2006 |
| 7094713 | Methods for improving the cracking resistance of low-k dielectric materials Methods for improving the mechanical properties of a CDO film are provided. The methods involve, for instance, providing either a dense CDO film or a porous CDO film in which the porogen has been removed followed by curing the CDO film at an elevated temperature usi... | 08/22/2006 |
| 7087471 | Locally thinned fins In a FinFET integrated circuit, the fins are formed with a reduced body thickness in the body area and then thickened in the S/D area outside the body to improve conductivity. The thickening is performed with epitaxial deposition while the lower portion of the gates... | 08/08/2006 |
| 7078296 | Self-aligned trench MOSFETs and methods for making the same Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOS... | 07/18/2006 |
| 7067890 | Thick oxide region in a semiconductor device A method of forming an oxide region in a semiconductor device includes the steps of forming a plurality of trenches in a semiconductor layer of the device, the trenches being formed in close relative proximity to one another, and oxidizing the semiconductor layer su... | 06/27/2006 |
| 7067874 | Semiconductor device including trench with at least one of an edge of an opening and a bottom surface being round A semiconductor device that includes an insulating substrate, a plurality of semiconductor layers arranged to be isolated from one another on the insulating substrate, and a semiconductor element independently provided on the semiconductor layers. Further, a trench ... | 06/27/2006 |
| 7049206 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 05/23/2006 |
| 7041575 | Localized strained semiconductor on insulator One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth withi... | 05/09/2006 |
| 7023051 | Localized strained semiconductor on insulator One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth withi... | 04/04/2006 |
| 7023068 | Method of etching a lateral trench under a drain junction of a MOS transistor In a MOS transistor, the drain capacitance is reduced by forming a lateral trench underneath the drain. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer. ... | 04/04/2006 |
| 7015549 | Integrated circuit structures including epitaxial silicon layers that extend from an active region through an insulation layer to a substrate An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active reg... | 03/21/2006 |
| 7008854 | Silicon oxycarbide substrates for bonded silicon on insulator A method for forming a semiconductor on insulator structure includes forming a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to... | 03/07/2006 |
| 6964907 | Method of etching a lateral trench under an extrinsic base and improved bipolar transistor In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer. ... | 11/15/2005 |
| 6929984 | Gettering using voids formed by surface transformation One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is an... | 08/16/2005 |
| 6927138 | Method of semiconductor device fabrication Provided is a method of semiconductor device fabrication capable of rounding the sharp edge portions of trenches so as to form device isolation regions having high electrical reliability. A semiconductor substrate comprising a lattice-strain relaxed silicon germaniu... | 08/09/2005 |
| 6924200 | Methods using disposable and permanent films for diffusion and implantation doping Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some... | 08/02/2005 |
| 6919258 | Semiconductor device incorporating a defect controlled strained channel structure and method of making the same A semiconductor device includes a single crystal substrate and a dielectric layer overlying the substrate. The dielectric layer includes at least one opening having a first portion and an overlying second portion. The first portion has a depth and width, such that a... | 07/19/2005 |
| 6914301 | CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-x... | 07/05/2005 |
| 6869856 | Process for manufacturing a semiconductor wafer integrating electronic devices including a structure for electromagnetic decoupling A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually a... | 03/22/2005 |
| 6703285 | Method for manufacturing capacitor structure, and method for manufacturing capacitor element An object of the present invention is to provide a method for manufacturing a capacitor structure that makes it possible to control the accumulation of electric charges on a top electrode film as a factor that brings about electrostatic breakdown in the i... | 03/09/2004 |
| 6693019 | METHOD OF MANUFACTURING AN ELECTRONIC POWER DEVICE MONOLITHICALLY INTEGRATED ON A SEMICONDUCTOR AND COMPRISING A FIRST POWER REGION, A SECOND REGION, AND AN ISOLATION STRUCTURE OF LIMITED PLANAR DIMENSION An electronic power device is integrated monolithically in a semiconductor substrate. The device has a first power region and a second region, each region including P/N junction formed of a first semiconductor region with a first type of conductivity, whi... | 02/17/2004 |
| 6670691 | Shallow trench isolation fill process A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in... | 12/30/2003 |
