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| Number | Title | Issue Date |
| 7943479 | Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flow A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is dep... | 05/17/2011 |
| 7781300 | Method for producing mixed stacked structures, different insulating areas and/or localised vertical electrical conducting areas The invention relates to a method for producing a semiconducting structure including: controlled formation, through a mask (31), in a first substrate (30) in a semiconducting material, of at least one first area in an... | 08/24/2010 |
| 7622359 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the Si... | 11/24/2009 |
| 7579254 | Process for realizing an integrated electronic circuit with two active layer portions having different crystal orientations A process for realizing an integrated electronic circuit makes it possible to obtain transistors with p-type conduction and transistors with n-type conduction, in respective active zones having crystal orientations adapted to each conduction type. In addition, each ... | 08/25/2009 |
| 7420202 | Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and... | 09/02/2008 |
| 7409660 | Method and end cell library for avoiding substrate noise in an integrated circuit A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input an integrated circuit design that includes at least a portion of a block for placement and routing on a substrate and an outer boundary of the block. An end cell is se... | 08/05/2008 |
| 7381627 | Dual wired integrated circuit chips A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with fir... | 06/03/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre... | 04/08/2008 |
| 7348251 | Modulated trigger device An integrated circuit structure, a trigger device and a method of electrostatic discharge protection, the integrated circuit structure including: a substrate having a top surface defining a horizontal direction, the substrate of a first dopant type; a first horizont... | 03/25/2008 |
| 7285477 | Dual wired integrated circuit chips A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with fir... | 10/23/2007 |
| 7276406 | Transistor structure with dual trench for optimized stress effect and method therefor A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semic... | 10/02/2007 |
| 7273788 | Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to... | 09/25/2007 |
| 7271074 | Trench insulation in substrate disks comprising logic semiconductors and power semiconductors Disclosed is a layer arrangement (4b, 5b, 9b, 10, 9a, 5a, 4a) within an insulating trench, which insulates circuits with little distortion while being suitable for electrically insul... | 09/18/2007 |
| 7268399 | Enhanced PMOS via transverse stress In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regio... | 09/11/2007 |
| 7265017 | Method for manufacturing partial SOI substrates There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region an... | 09/04/2007 |
| 7262428 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 08/28/2007 |
| 7262109 | Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semicond... | 08/28/2007 |
| 7229892 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device, includes preparing a semiconductor substrate, bonding a first semiconductor layer onto a part of the semiconductor substrate with a first insulating layer interposed therebetween, forming a second insulating layer on... | 06/12/2007 |
| 7226816 | Method of forming connection and anti-fuse in layered substrate such as SOI An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as... | 06/05/2007 |
| 7220655 | Method of forming an alignment mark on a wafer, and a wafer comprising same Disclosed herein is a method comprised of providing a wafer comprised of a bulk substrate, an insulating layer positioned above the bulk substrate, and a semiconducting layer positioned above the insulating layer, forming an opening in the semiconducting layer and t... | 05/22/2007 |
| 7217604 | Structure and method for thin box SOI device A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the devic... | 05/15/2007 |
| 7199017 | Methods of forming semiconductor circuitry The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion... | 04/03/2007 |
| 7192840 | Semiconductor device fabrication method using oxygen ion implantation A method of fabricating a semiconductor device having a silicon layer disposed on an insulating film. Oxygen ions are implanted into selected parts of the silicon layer, which are then oxidized to form isolation regions dividing the silicon layer into a plurality of... | 03/20/2007 |
| 7187035 | Semiconductor device comprising multiple layers with trenches formed on a semiconductor substrate A method of manufacturing a semiconductor device substrate is disclosed, which comprises forming a mask layer patterned on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor laye... | 03/06/2007 |
| 7183180 | Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device A method of simultaneously fabricating at least two semiconductor devices, at least one of which is a nanocrystal memory and at least one of which is a non-nonocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semico... | 02/27/2007 |
| 7166519 | Method for isolating semiconductor devices with use of shallow trench isolation method The present invention relates to a method for isolating semiconductor devices. The method includes the steps of: forming a patterned pad nitride layer pattern to open at least one isolation region on the substrate; forming a first trench and a second trench by etchi... | 01/23/2007 |
| 7164294 | Method for forming programmable logic arrays using vertical gate transistors One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical fu... | 01/16/2007 |
| 7153753 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 12/26/2006 |
| 7153731 | Method of forming a field effect transistor with halo implant regions A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed withi... | 12/26/2006 |
| 7148511 | Active matrix substrate, electro-optical device, electronic device, and method for manufacturing an active matrix substrate An active matrix substrate includes a load circuit including a first active element performing a switching operation of a load, the first active element including a semiconductor film of a substantially polycrystalline state; a drive circuit including a second activ... | 12/12/2006 |
| 7148543 | Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer lo... | 12/12/2006 |
| 7144764 | Method of manufacturing semiconductor device having trench isolation The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitri... | 12/05/2006 |
| 7132347 | Semiconductor device with trench structure and method for manufacturing the same A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define siz... | 11/07/2006 |
| 7128825 | Method and composition for polishing a substrate Polishing compositions and methods for removing conductive materials from a substrate surface are provided. In one aspect, a composition includes an acid based electrolyte system, one or more chelating agents, one or more corrosion inhibitors, one or more inorganic ... | 10/31/2006 |
| 7118990 | Methods for making large dimension, flexible piezoelectric ceramic tapes A method for producing a detection/test tape includes depositing a material onto a surface of at least one first substrate to form a plurality of element structures. Electrodes are deposited on a surface of each of the plurality of element structures, and the elemen... | 10/10/2006 |
| 7115463 | Patterning SOI with silicon mask to create box at different depths The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask hav... | 10/03/2006 |
| 7115480 | Micromechanical strained semiconductor by wafer bonding One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a first semiconductor wafer such that the surface of the first semiconductor wafer h... | 10/03/2006 |
| 7105389 | Method of manufacturing semiconductor device having impurity region under isolation region In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film | 09/12/2006 |
| 7103316 | Method and apparatus determining the presence of interference in a wireless communication channel A method and apparatus for estimating the presence of RF interference in a wireless data channel is described. The method and apparatus comprises a set of identical tracking/register (T/R) filter blocks, each T/R filter block associated and corresponding to an RF ch... | 09/05/2006 |
