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| Number | Title | Issue Date |
| 8048759 | Semiconductor device and method of manufacturing the same The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the S... | 11/01/2011 |
| 8039357 | Integrated circuitry and methods of forming a semiconductor-on-insulator substrate Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of mater... | 10/18/2011 |
| 8030169 | SOI substrate and manufacturing method thereof An object is to provide an SOI substrate provided with a semiconductor layer which can be used practically even when a glass substrate is used as a base substrate. Another object is to provide a semiconductor device having high reliability using such an SOI substrat... | 10/04/2011 |
| 7951683 | In-situ process layer using silicon-rich-oxide for etch selectivity in high AR gapfill In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots is provided. ... | 05/31/2011 |
| 7927961 | Selective etching method and method for forming an isolation structure of a memory device A disclosed selective etching method comprises mixing a polymer with carbon nanotubes, applying the mixture to an etching target layer to form a carbon nanotube-polymer composite layer, forming a hard mask by patterning the carbon nanotube-polymer composite layer, s... | 04/19/2011 |
| 7892938 | Structure and method for III-nitride monolithic power IC III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown perfor... | 02/22/2011 |
| 7439153 | Semiconductor device and manufacturing method thereof for reducing the area of the memory cell region A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the nec... | 10/21/2008 |
| 7432149 | CMOS on SOI substrates with hybrid crystal orientations Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming ... | 10/07/2008 |
| 7425495 | Method of manufacturing semiconductor substrate and semiconductor device A method of manufacturing a semiconductor substrate and semiconductor device is disclosed and comprises forming a first monocrystalline semiconductor layer on a semiconductor base material, forming a second monocrystalline semiconductor layer covering the first mono... | 09/16/2008 |
| 7420202 | Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and... | 09/02/2008 |
| 7410858 | Isolation structure configurations for modifying stresses in semiconductor devices An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention i... | 08/12/2008 |
| 7390696 | Wafer, semiconductor device, and fabrication methods therefor In order to fabricate a semiconductor device that can perform at its full capacity, in which (i) a single-crystal silicon integrated circuit is formed on an insulating substrate without an adhesive agent, and (ii) an active region of the single-crystal integrated ci... | 06/24/2008 |
| 7384857 | Method to fabricate completely isolated silicon regions The construction of Shallow Trench Isolation, STI, regions is integrated in to a SIMOX fabrication process for a Silicon On Insulator, SOI, wafer. Prior to the beginning of the SOI process, a preferred nitrogen (N2) implant is applied to the silicon wafer... | 06/10/2008 |
| 7382031 | Component including a fixed element that is in a silicon layer and is mechanically connected to a substrate via an anchoring element and method for its manufacture A method and device are for anchoring fixed structural elements and, e.g., for anchoring electrodes for components, e.g., SOI wafer components, whose component structure is formed in a silicon layer on top of a substrate used as support. The fixed element may be mec... | 06/03/2008 |
| 7368790 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 05/06/2008 |
| 7358586 | Silicon-on-insulator wafer having reentrant shape dielectric trenches A bonded SOI wafer and a method for forming a bonded SOI wafer are provided. According to the disclosed method, a first semiconductor wafer is provided, having a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric fil... | 04/15/2008 |
| 7358191 | Method for decreasing sheet resistivity variations of an interconnect metal layer According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenche... | 04/15/2008 |
| 7358161 | Methods of forming transistor devices associated with semiconductor-on-insulator constructions The invention encompasses a method of forming a semiconductor on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is fo... | 04/15/2008 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre... | 04/08/2008 |
| 7351616 | Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate and method for manufacturing semiconductor device A semiconductor substrate comprising: a semiconductor base; dielectric layers of mutually different film thicknesses formed on the semiconductor base; and semiconductor layers of mutually different film thicknesses formed on the dielectric layers. ... | 04/01/2008 |
| 7348254 | Method of fabricating fin field-effect transistors A method of fabricating a fin field-effect transistor that may enable a reduction in the number of process steps, by forming the fin structure by etching away a predetermined thickness of an element isolation layer. The method includes steps of sequentially forming ... | 03/25/2008 |
| 7348255 | Semiconductor device and method for fabricating a semiconductor device A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second in... | 03/25/2008 |
| 7335568 | Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors abov... | 02/26/2008 |
| 7335599 | Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layer... | 02/26/2008 |
| 7329609 | Substrate processing method and substrate processing apparatus In a substrate processing apparatus, a control electrode (131) separates a process space (11C) including a substrate to be processed and a plasma formation space (11B) not including the substrate. The control electrode includes a conductive memb... | 02/12/2008 |
| 7323394 | Method of producing element separation structure A method of producing an element separation structure includes the steps of: forming a first thermal oxide film on the substrate; forming a silicon nitride film on the first thermal oxide film; removing the first thermal oxide film and the silicon nitride film in an... | 01/29/2008 |
| 7323387 | Method to make nano structure below 25 nanometer with high uniformity on large scale A method of making a nano structure smaller than 25 nanometers utilizing atomic layer deposition, planarizing, and etching techniques. ... | 01/29/2008 |
| 7316979 | Method and apparatus for providing an integrated active region on silicon-on-insulator devices A method and apparatus for providing integrated active regions on silicon-on-insulator (SOI) devices by oxidizing a portion of the active layer. When the active layer of the SOI wafer is relatively thick, such as about 200 Å to 1000 Å or greater, the etching pro... | 01/08/2008 |
| 7316959 | Semiconductor device and method for fabricating the same The semiconductor device comprises a semiconductor layer 18 formed on an insulation layer 16, a gate electrode 22 formed on the semiconductor layer with a gate insulation film 20 formed therebetween, a source/drain region 24 formed... | 01/08/2008 |
| 7312128 | Selective epitaxy process with alternating gas supply In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amo... | 12/25/2007 |
| 7302857 | Method for reducing the temperature dependence of a capacitive sensor and a capacitive sensor construction A method of manufacturing a sensor including forming an insulating layer on top of a conductive substrate, and forming a conducting electrode on top of the insulating layer. Further, the insulating layer is formed to include support areas formed at edges of the cond... | 12/04/2007 |
| 7297608 | Method for controlling properties of conformal silica nanolaminates formed by rapid vapor deposition A method employing atomic layer deposition rapid vapor deposition (RVD) conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film is then annealed using a high density plasma (HDP) at a temperature under 500°... | 11/20/2007 |
| 7294573 | Method for controlling poly 1 thickness and uniformity in a memory array fabrication process According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surface... | 11/13/2007 |
| 7294536 | Process for manufacturing an SOI wafer by annealing and oxidation of buried channels A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.... | 11/13/2007 |
| 7291541 | System and method for providing improved trench isolation of semiconductor devices A system and method is disclosed for providing improved trench isolation of semiconductor devices. An isolation trench of the present invention is manufactured as follows. A substrate of a semiconductor device is provided and a trench is etched in the substrate. The... | 11/06/2007 |
| 7288462 | Buffer zone for the prevention of metal migration Particle migration, such as silver electro-migration, on a flat ceramic surface is effectively eliminated by an upward vertical barrier formed on the surface or a groove formed in the surface between two silver conductors. ... | 10/30/2007 |
| 7285480 | Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FE... | 10/23/2007 |
| 7279769 | Semiconductor device and manufacturing method thereof To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an ele... | 10/09/2007 |
| 7276774 | Trench isolation structures for integrated circuits A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no mo... | 10/02/2007 |
| 7273904 | Nanocrystals in ligand boxes exhibiting enhanced chemical, photochemical, and thermal stability, and methods of making the same Dendron ligands or other branched ligands with cross-linkable groups were coordinated to colloidal inorganic nanoparticles, including nanocrystals, and substantially globally cross-linked through different strategies, such as ring-closing metathesis (RCM), dendrimer... | 09/25/2007 |
