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| Number | Title | Issue Date |
| 7651921 | Semiconductor device having a frontside contact and vertical trench isolation and method of fabricating same There is a method of forming a contact post and surrounding isolation trench in a semiconductor-on-insulator (SOI) substrate. The method comprises etching a contact hole and surrounding isolation trench from an active layer of the substrate to the insulating layer, ... | 01/26/2010 |
| 7538008 | Method for producing a layer structure A layer structure comprising a smoothed interlayer and an overlying layer applied on the interlayer, wherein the interlayer is treated with a gaseous etchant containing hydrogen fluoride, a material removal being obtained thereby and the interlayer being smoothed. | 05/26/2009 |
| 7501327 | Fabricating method of semiconductor optical device for flip-chip bonding Disclosed is a method for manufacturing a semiconductor optical device for flip-chip bonding. The method includes the steps of: etching an active layer and clad which are sequentially stacked on a semiconductor substrate into first and second alignment keys and an o... | 03/10/2009 |
| 7432171 | Silicon carbide and related wide-bandgap transistors on semi-insulating epitaxy for high-speed, high-power applications A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substr... | 10/07/2008 |
| 7432173 | Methods of fabricating silicon-on-insulator substrates having a laser-formed single crystalline film In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor... | 10/07/2008 |
| 7364958 | CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hyb... | 04/29/2008 |
| 7273904 | Nanocrystals in ligand boxes exhibiting enhanced chemical, photochemical, and thermal stability, and methods of making the same Dendron ligands or other branched ligands with cross-linkable groups were coordinated to colloidal inorganic nanoparticles, including nanocrystals, and substantially globally cross-linked through different strategies, such as ring-closing metathesis (RCM), dendrimer... | 09/25/2007 |
| 7273788 | Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to... | 09/25/2007 |
| 7223162 | Holder for wafers The present invention provides a holder (20) for wafers (14) which makes it possible to more easily manipulate the wafer (14) and makes it more suitable than prior art devices for to liquid handling, wafer handling and on-wafer manipulation of s... | 05/29/2007 |
| 7202124 | Strained gettering layers for semiconductor processes A method and structure for forming semiconductor structures using tensilely strained gettering layers. The method includes forming a donor wafer comprising a tensilely strained gettering layer disposed over a substrate, and at least one material layer disposed over ... | 04/10/2007 |
| 7160786 | Silicon on insulator device and layout method of the same A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped reg... | 01/09/2007 |
| 7109072 | Semiconductor material, field effect transistor and manufacturing method thereof The silicon wires formed around metal particles by crystal growth have the problem of metal pollution. For its solution, in the present invention, a silicon bridge is formed through standard silicon processes such as the lithography and the wet etching using hydrofl... | 09/19/2006 |
| 7105426 | Method of forming a semi-insulating region A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semic... | 09/12/2006 |
| 7008854 | Silicon oxycarbide substrates for bonded silicon on insulator A method for forming a semiconductor on insulator structure includes forming a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to... | 03/07/2006 |
| 6936504 | Poly-silicon thin film transistor having back bias effects and fabrication method thereof A poly-silicon (poly-Si) thin film transistor (TFT) having a back bias effect is provided in order to enhance characteristics of a leakage current, a sub-threshold slope, and an on-current. The poly-Si TFT includes a glass substrate, an island type buried electrode ... | 08/30/2005 |
| 6927144 | Method for manufacturing buried insulating layer type single crystal silicon carbide substrate Provided is a manufacturing method of a buried insulating layer type semiconductor silicon carbide substrate excellent in flatness of an interfaces in contact the insulating layer and a manufacturing device thereof. In the manufacturing device, an SOI substrate havi... | 08/09/2005 |
| 6900108 | High temperature sensors utilizing doping controlled, dielectrically isolated beta silicon carbide (SiC) sensing elements on a specifically selected high temperature force collecting membrane Semiconductor devices useful in high temperature sensing applications include a silicon carbide substrate, a silicon dioxide layer, and an outer layer of crystalline doped silicon carbide. The device is a 3C—SiC/SiO2/SiC structure. This structure can be... | 05/31/2005 |
| 6706542 | Application of InAIAs double-layer to block dopant out-diffusion in III-V device Fabrication The present invention relates to a multi-layer dopant barrier and its method of fabrication for use in semiconductor structures. In an illustrative embodiment, the multi-layer dopant barrier is disposed between a first doped layer and a second doped layer. The multi... | 03/16/2004 |
| 6686647 | Gunn diode and method of manufacturing the same Indium phosphor (InP) Gunn diode that realizes improvements in thermal characteristics, yield factor of good products and easy assembly to planar circuits is provided. In a Gunn diode of the present invention, contact layers are interposing an active laye... | 02/03/2004 |
| 6635550 | Semiconductor on insulator device architecture and method of construction An SOI architecture is provided that comprises an inner substrate 10 which has a buried conductor layer 12 formed on an outer surface thereof. A bonding layer 14 is used to provide a cohesive bond with a buried insulator layer 18. The semiconductor device... | 10/21/2003 |
| 6537890 | Poly-silicon thin film transistor having back bias effects and fabrication method thereof A poly-silicon (poly-Si) thin film transistor (TFT) having a back bias effect is provided in order to enhance characteristics of a leakage current, a sub-threshold slope, and an on-current. The poly-Si TFT includes a glass substrate, an island type buried... | 03/25/2003 |
| 6358814 | Method for manufacturing semiconductor devices having an epitaxial layer and wafer alignment marks To control the positional relation between semiconductor regions formed on an epitaxial layer after the epitaxial layer is formed with high accuracy in a method for manufacturing semiconductor devices in which a plurality of semiconductor regions are form... | 03/19/2002 |
| 6191006 | Method of bonding a III-V group compound semiconductor layer on a silicon substrate Prior to a heat treatment for bonding a III-V group compound semiconductor layer on a silicon substrate, a thermal stress relaxation layer is provided between the silicon layer and the III-V group compound semiconductor layer thermal stress relaxation lay... | 02/20/2001 |
| 6121097 | Semiconductor device manufacturing method A polysilicon film is deposited in a trench formed in a silicon element substrate. The polysilicon film in the trench and on the silicon element substrate is anisotropically etched, so that the film remains on the side wall of the trench. The polysilicon ... | 09/19/2000 |
| 6071753 | Method of producing a solar cell A solar cell and a method of producing the same which realizes electrical separation of the p n junction in a simple manner, and a method of producing a semiconductor device a method of producing a semiconductor device in which an electrode is formed by u... | 06/06/2000 |
| 6046109 | Creation of local semi-insulating regions on semiconductor substrates The present invention solves the problem of how to form local regions of semi-insulating material within a single crystal substrate. It does this by irradiating the semiconductor with a high energy beam capable of producing radiation damage along its path... | 04/04/2000 |
| 6030884 | Method of bonding a III-V group compound semiconductor layer on a silicon substrate Prior to a heat treatment for bonding a III-V group compound semiconductor layer on a silicon substrate, a thermal stress relaxation layer is provided between the silicon layer and the III-V group compound semiconductor layer thermal stress relaxation lay... | 02/29/2000 |
| 5856231 | Process for producing high-resistance silicon carbide A process for producing high-resistance SiC from low-resistance SiC starting material. The flat (shallow) donor levels of a prevailing nitrogen impurity are overcompensated by admixture of a trivalent doping element with the concentration of the doping el... | 01/05/1999 |
| 5786261 | Method for fabricating semiconductor device having device isolation layer First, a non-doped AlGaAs layer and an n-GaAs layer serving as a conductive layer are formed in order on the surface of a semi-insulating GaAs substrate. Then, a photoresist film having an opening in its predetermined position is formed on the surface of ... | 07/28/1998 |
| 5728623 | Method of bonding a III-V group compound semiconductor layer on a silicon substrate Prior to a heat treatment for bonding a III-V group compound semiconductor layer on a silicon substrate, a thermal stress relaxation layer is provided between the silicon layer and the III-V group compound semiconductor layer thermal stress relaxation lay... | 03/17/1998 |
| 5705408 | Method for forming semiconductor integrated circuit using monolayer epitaxial growth A semiconductor integrated circuit device including: an off-substrate having a semiconductor surface with a plurality of steps each having a height of one monolayer and extending in one direction; a wiring layer formed on the semiconductor surface of the ... | 01/06/1998 |
| 5702975 | Method for isolating semiconductor device A method for isolating a semiconductor device is disclosed including the steps of sequentially growing a plurality of material layers on a semiconductor substrate, etching the material layers down to a predetermined depth of the substrate to thereby defin... | 12/30/1997 |
| 5637513 | Fabrication method of semiconductor device with SOI structure A fabrication method of a semiconductor device that can realize a semiconductor device having an improved radiation performance of heat together with a low parasitic capacitance between a semiconductor substrate and a conductor of the device. An SOI struc... | 06/10/1997 |
| 5633174 | Type silicon material with enhanced surface mobility A new-type silicon material is produced by hydrogen ion implantation and subsequent annealing, the annealing being preferably in two steps. The present invention raises surface mobility of a silicon wafer and produces a buried high-resistivity layer benea... | 05/27/1997 |
| 5610095 | Monolithically integrated circuits having dielectrically isolated, electrically controlled optical devices and process for fabricating the same A fabrication technique for improved dielectric isolation of adjacent, electronic devices or electrically controllable optical devices provides an inter-device resistance in excess of 1 MΩ. Strips of a silicon oxide material, such as SiO2, are... | 03/11/1997 |
| 5599389 | Compound semiconductor and method of manufacturing the same According to this invention, there is provided a compound semiconductor substrate including, on a compound semiconductor base containing a high-concentration impurity, a high-resistance single-crystal layer consisting of the same compound semiconductor as... | 02/04/1997 |
| 5552335 | Acoustic charge transport integrated circuit process A process for fabricating an acoustic charge transport (ACT) integrated circuit, comprises the steps of providing a semi-insulating wafer; providing an epitaxial layer with a thickness and carrier concentration appropriate for an ACT device on the semi-in... | 09/03/1996 |
| 5523241 | Method of making infrared detector with channel stops Channel stops for MIS infrared photodetector devices in Hg1-x Cdx Te by lattice damage (454) between and automatically aligned to MIS gates (408). Also, field plates and guard rings are automatically aligned to MIS gates.... | 06/04/1996 |
| 5518951 | Method for making thin film piezoresistive sensor Semiconductor piezoresistive sensors are fabricated by a process that includes plasma enhanced chemical vapor deposition and selective laser recrystallization. An insulating dielectric layer is first vapor deposited on a flexible substrate. A layer of hig... | 05/21/1996 |
| 5508210 | Element isolating method for compound semiconductor device A method of element isolation includes implanting ions in a compound semiconductor substrate at the periphery of a semiconductor device in the substrate to produce a first insulating region having a region of maximum implanted ion concentration within a b... | 04/16/1996 |
