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3M employee and church chorister Art Fry needed something to temporarily mark pages in his hymnal. He was in luck because his colleague, Spencer Silver, accidentally developed a glue that was too weak for other purposes. After initially discouraging consumer response, Post-it Notes became a hit in 1979.
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| Number | Title | Issue Date |
| 8124494 | Method for reshaping silicon surfaces with shallow trench isolation A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in... | 02/28/2012 |
| 7888232 | Method for producing a protective structure A protective structure is produced by providing a semiconductor substrate with a doping of a first conductivity type. A semiconductor layer with a doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping... | 02/15/2011 |
| 7871893 | Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic ... | 01/18/2011 |
| 7829429 | Semiconductor device having localized insulated block in bulk substrate and related method One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first por... | 11/09/2010 |
| 7824999 | Method for enhancing field oxide A CMOS device with polysilicon protection tiles is shown in FIG. 2. LOCOS regions 12.1 and 12.2 separate adjacent active regions 16.1 from 16 and 18.1 from 18, respectively. On the upper surface of the LOCOS regions | 11/02/2010 |
| 7807543 | Methods of manufacturing trench isolation structures using selective plasma ion immersion implantation and deposition (PIIID) A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of a... | 10/05/2010 |
| 7803689 | Semiconductor device manufactured with a double shallow trench isolation process A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the... | 09/28/2010 |
| 7776708 | System and method for providing a nitride cap over a polysilicon filled trench to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. A composite layer stack is formed over th... | 08/17/2010 |
| 7763521 | Metal wiring and method for forming the same A metal wiring and method for forming the same are provided. A first conductive layer is formed on a semiconductor substrate, and an insulating layer is formed on the first conductive layer. A via and a trench are formed in the insulating layer, and a second conduct... | 07/27/2010 |
| 7727851 | Method of measuring shifted epitaxy layer by buried layer A method of measuring a shifted extent of a shifted epitaxy layer by an N+ buried layer using difference between contact resistances is described. An N-type buried layer comprising a stepped portion is formed at a P-type substrate. An epitaxy layer is for... | 06/01/2010 |
| 7704849 | Methods of forming trench isolation in silicon of a semiconductor substrate by plasma A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the sem... | 04/27/2010 |
| 7687367 | Manufacture method for semiconductor device having field oxide film On the principal surface of a silicon substrate, a side spacer made of silicon nitride is formed on the side wall of a lamination including a silicon oxide film, a silicon nitride film and a silicon oxide film. Thereafter, a channel stopper ion doped region is forme... | 03/30/2010 |
| 7622358 | Semiconductor device with semi-insulating substrate portions and method for forming the same A method for forming semi-insulating portions in a semiconductor substrate provides depositing a hardmask film over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The hardmask is patterned creat... | 11/24/2009 |
| 7592234 | Method for forming a nitrogen-containing gate insulating film A method for forming a nitrogen-containing gate insulating film includes the steps of forming a silicon oxide film on a silicon substrate, nitriding the top portion of the silicon oxide film to form a thin silicon nitride layer, and forming a silicon nitride film on... | 09/22/2009 |
| 7550361 | Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of featu... | 06/23/2009 |
| 7521331 | High dielectric film and related method of manufacture A method of forming a high dielectric film for a semiconductor device comprises supplying a first source gas to a reaction chamber during a first time interval, supplying a first reactant gas to the reaction chamber during a second time interval after the first time... | 04/21/2009 |
| 7446015 | Semiconductor device and method for manufacturing the same A semiconductor device includes a circuit formation region which is formed in a semiconductor substrate and includes a plurality of element formation regions surrounded by isolation regions, respectively. A stress effect relief region of a predetermined width is for... | 11/04/2008 |
| 7432593 | Semiconductor package assembly and method for electrically isolating modules A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394. ... | 10/07/2008 |
| 7429518 | Method for forming shallow trench isolation of semiconductor device A shallow trench isolation well is formed to be very thin in a highly integrated semiconductor device. When critical dimension (CD) is small, it is difficult to reduce the width of the photosensitive layer pattern for forming a trench to no more than a predetermined... | 09/30/2008 |
| 7414299 | Semiconductor package assembly and method for electrically isolating modules A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394. ... | 08/19/2008 |
| 7407826 | Vacuum packaged single crystal silicon device A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anch... | 08/05/2008 |
| 7396733 | Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device A method for manufacturing a semiconductor substrate, including: forming a first semiconductor layer on a semiconductive base; forming a second semiconductor layer, having a smaller etching selection ratio than that of the first semiconductor layer, on the first sem... | 07/08/2008 |
| 7387918 | Method of forming a silicon controlled rectifier structure with improved punch through resistance When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the recti... | 06/17/2008 |
| 7381625 | Deterministic process for constructing nanodevices A method is provided for constructing a nanodevice. The method includes: fabricating an electrode on a substrate; forming a nanogap across the electrode; dispersing a plurality of nanoobjects onto the substrate using electrophoresis; and pushing one of the nanoobjec... | 06/03/2008 |
| 7372730 | Method of reading NAND memory to compensate for coupling between storage elements A method for reading a non-volatile memory arranged in columns and rows which reduces adjacent cell coupling, sometimes referred to as the Yupin effect. The method includes the steps of: selecting a bit to be read in a word-line; reading an adjacent word line writte... | 05/13/2008 |
| 7367119 | Method for forming a reinforced tip for a probe storage device Systems and methods in accordance with the present invention can include a tip contactable with a media. In an embodiment, the tip comprises a substantially hollow structure formed of a metal. The tip can be formed by depositing a first metal layer over silicon ther... | 05/06/2008 |
| 7365378 | MOSFET structure with ultra-low K spacer A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall... | 04/29/2008 |
| 7361572 | STI liner modification method A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further i... | 04/22/2008 |
| 7354821 | Methods of fabricating trench capacitors with insulating layer collars in undercut regions Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the firs... | 04/08/2008 |
| 7354834 | Semiconductor devices and methods to form trenches in semiconductor devices Semiconductor devices and methods of fabricating the same are disclosed. One example method may include forming sequentially a pad oxide film and a silicon nitride film on an entire surface of a semiconductor substrate, forming the trench by etching the silicon nitr... | 04/08/2008 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre... | 04/08/2008 |
| 7350281 | Method of protecting a capacitor An electric device includes an electric element, such as a wound film capacitor, with power input and output leads. The electric element includes a coating layer of parylene that provides moisture resistance and low gas and moisture permeability to protect the elect... | 04/01/2008 |
| 7352019 | Capacitance reduction by tunnel formation for use with a semiconductor device A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectr... | 04/01/2008 |
| 7352001 | Method of editing a semiconductor die Resistance and capacitance are added to a prototype die to fix or identify performance issues with the integrated circuit formed in the die by forming a thin piece of silicon on the top surface of the die. For resistance, vias are formed to regions on the metal trac... | 04/01/2008 |
| 7348281 | Method of filling structures for forming via-first dual damascene interconnects A method of forming via-first, dual damascene interconnect structures by using a gap-filling, bottom anti-reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating ... | 03/25/2008 |
| 7344981 | Plated terminations A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of internal electrode elements and a plurality of internal anchor tabs. Portions of the internal electrode elements and anchor tabs are exposed along the periphe... | 03/18/2008 |
| 7338880 | Method of fabricating a semiconductor device A method of fabricating a semiconductor device includes steps of forming at least one shallow-trench isolation region in a semiconductor substrate; forming a photoresist pattern for blocking a photodiode region; sequentially implanting dopant ions and boron ions int... | 03/04/2008 |
| 7338869 | Semiconductor device and its manufacturing method A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high voltage resistancehigh blocking voltage and high channel mobility is manufactured by optimizing the... | 03/04/2008 |
| 7335564 | Method for forming device isolation layer of semiconductor device A method for forming a device isolation device of a semiconductor device is disclosed. The method includes the steps of forming a moat pattern for forming a trench on a semiconductor substrate, forming a trench by etching the semiconductor substrate to a predetermin... | 02/26/2008 |
| 7336524 | Atomic probes and media for high density data storage A device in accordance with embodiments of the present invention comprises a contact probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the contact probe can include a silicon core having a conductive coating. Contact pro... | 02/26/2008 |
