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| Number | Title | Issue Date |
| 8076213 | Method for fabricating a metal-insulator-metal capacitor A method for fabricating a metal-insulator-metal (MIM) capacitor includes providing a substrate comprising a bottom electrode, forming a dielectric layer positioned on the bottom electrode, and forming a top electrode positioned on the dielectric layer. The dielectr... | 12/13/2011 |
| 7842581 | Methods of forming metal layers using oxygen gas as a reaction source and methods of fabricating capacitors using such metal layers When a metal layer formed by reaction of a metal source and an oxygen (O2) source is deposited, oxidization of a conductive layer disposed under or on the metal layer can be reduced and/or prevented by a method of forming the metal layer and a method of f... | 11/30/2010 |
| 7754577 | Method for fabricating capacitor A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a sto... | 07/13/2010 |
| 7709343 | Use of a plasma source to form a layer during the formation of a semiconductor device A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further com... | 05/04/2010 |
| 7687366 | Pre-patterned thin film capacitor and method for embedding same in a package substrate An embedded passive structure, its method of formation, and its integration onto a substrate during fabrication are disclosed. In one embodiment, the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted on... | 03/30/2010 |
| 7553738 | Method of fabricating a microelectronic device including embedded thin film capacitor by over-etching thin film capacitor bottom electrode and microelectronic device made according to the method A microelectronic device, a method of fabricating the device, and a system including the device. The method includes: providing a substrate including an underlying conductive layer and a polymer build-up layer overlying the underlying conductive layer; providing a p... | 06/30/2009 |
| 7550360 | Solid electrolytic capacitor manufacturing method capable of easily and properly connecting anode electrode portion In a method of manufacturing a solid electrolytic capacitor, at first, an anodic oxide film is formed on the surface of an aluminum base. Then, a solid electrolyte layer is formed of a conductive polymer or the like on the anodic oxide film. Then, a cathode electrod... | 06/23/2009 |
| 7456078 | Thin-film capacitor and method for fabricating the same, electronic device and circuit board The thin-film capacitor comprises a capacitor part 20 formed over a base substrate 10 and including a first capacitor electrode 14, a capacitor dielectric film 16 formed over the first capacitor electrode 14, and a second capacitor... | 11/25/2008 |
| 7446014 | Nanoelectrochemical cell A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface... | 11/04/2008 |
| 7439126 | Method for manufacturing semiconductor memory A method for manufacturing a semiconductor memory having a memory cell selection transistor and a capacitor, comprises a step of forming a polysilicon plug having a large-diameter portion on a side of the capacitor, a step of forming a hole reaching the large-diamet... | 10/21/2008 |
| 7429535 | Use of a plasma source to form a layer during the formation of a semiconductor device A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further com... | 09/30/2008 |
| 7422954 | Method for fabricating a capacitor structure A capacitor structure is described, including a substrate, a first metal layer in the substrate, an etching stop layer on the substrate having therein an opening that exposes a portion of the first metal layer, a connection layer on the portion of the first metal la... | 09/09/2008 |
| 7417275 | Capacitor pair structure for increasing the match thereof A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ra... | 08/26/2008 |
| 7407862 | Method for manufacturing ferroelectric memory device A method for manufacturing a ferroelectric memory device includes the steps of forming an active element on a substrate; forming an interlayer dielectric film on the substrate; forming a contact hole in the interlayer dielectric film; forming, in the contact hole, a... | 08/05/2008 |
| 7393742 | Semiconductor device having a capacitor and a fabrication method thereof In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate and an insulating layer on the semiconductor substrate, a contact plug electrically connected to the semiconductor substra... | 07/01/2008 |
| 7361549 | Method for fabricating memory cells for a memory device The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (100), in which method a shaping layer (104) is provided and is patterned in such a manner that vertical trench struc... | 04/22/2008 |
| 7354843 | Method of forming a capacitor that includes forming a bottom electrode in a strained silicon layer A decoupling capacitor is formed in a semiconductor substrate that includes a strained silicon layer. A substantially flat bottom electrode is formed in a portion of the strained silicon layer and a capacitor dielectric overlying the bottom electrode. A substantiall... | 04/08/2008 |
| 7348194 | Electrode compositions containing carbon nanotubes for solid electrolyte capacitors An improved capacitor with an anode with an anode wire and an oxide layer on the surface of the anode. A cathode layer is exterior to the oxide layer. A carbon conductive layer is exterior to the cathode layer wherein the cathode layer comprises 5-75 wt % resin and ... | 03/25/2008 |
| 7338879 | Method of fabricating a semiconductor device having dual stacked MIM capacitor Semiconductor devices having a dual stacked MIM capacitor and methods of fabricating the same are disclosed. The semiconductor device includes a dual stacked MIM capacitor formed on the semiconductor substrate. The dual stacked MIM capacitor includes a lower plate p... | 03/04/2008 |
| 7339222 | Method for determining wordline critical dimension in a memory array and related structure According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between tw... | 03/04/2008 |
| 7329572 | Method of forming PIP capacitor A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor includes the steps of forming a lower electrode of a first polysilicon layer over a semiconductor substrate, forming a dielectric layer over the lower electrode, forming a second polysilicon lay... | 02/12/2008 |
| 7319069 | Structure having pores, device using the same, and manufacturing methods therefor A minute structure is provided in which electroconductive paths are only formed in nanoholes, and a material is filled in the nanoholes, which are disposed in a specific area, by using the electroconductive paths. The minute structure comprising pores comprises a) a... | 01/15/2008 |
| 7316954 | Methods of fabricating integrated circuit devices that utilize doped poly-SiGeconductive plugs as interconnects The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating ... | 01/08/2008 |
| 7312121 | Method of manufacturing a semiconductor memory device Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer co... | 12/25/2007 |
| 7298000 | Conductive container structures having a dielectric cap Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conducti... | 11/20/2007 |
| 7294578 | Use of a plasma source to form a layer during the formation of a semiconductor device A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further com... | 11/13/2007 |
| 7294545 | Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilico... | 11/13/2007 |
| 7279432 | System and method for forming an integrated barrier layer An apparatus and method for forming an integrated barrier layer on a substrate is described. The integrated barrier layer comprises at least a first refractory metal layer and a second refractory metal layer. The integrated barrier layer is formed using a dual-mode ... | 10/09/2007 |
| 7276751 | Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same The present invention relates to a semiconductor device that contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located i... | 10/02/2007 |
| 7273814 | Method for forming a ruthenium metal layer on a patterned substrate A method for forming a ruthenium metal layer includes providing a patterned substrate in a process chamber of a deposition system, where the patterned substrate contains one or more vias or trenches, or combinations thereof, depositing a first ruthenium metal layer ... | 09/25/2007 |
| 7268026 | Method for manufacturing both a semiconductor crystalline film and semiconductor device A method of forming a crystal grain for use in a semiconductor manufacturing process, the method including the steps of forming an oxide silicon film on a glass substrate, etching at least one hole at a predetermined location in the oxide silicon film, forming an am... | 09/11/2007 |
| 7265406 | Capacitor with conducting nanostructure The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper con... | 09/04/2007 |
| 7264846 | Ruthenium layer formation for copper film deposition A method of ruthenium layer formation for high aspect ratios, interconnect features is described. The ruthenium layer is formed using a cyclical deposition process. The cyclical deposition process comprises alternately adsorbing a ruthenium-containing precursor and ... | 09/04/2007 |
| 7253052 | Method for forming a storage cell capacitor compatible with high dielectric constant materials Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion o... | 08/07/2007 |
| 7232736 | Semiconductor devices with capacitors of metal/insulator/metal structure and methods for forming the same Semiconductor devices with copper interconnections and MIM capacitors and methods of fabricating the same are provided. The device includes a lower electrode composed of a first copper layer. A first insulation layer covers a lower electrode. A window is formed in t... | 06/19/2007 |
| 7229904 | Method for forming landing plug contacts in semiconductor device Disclosed is a method for forming landing plug contacts in a semiconductor device. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer on the... | 06/12/2007 |
| 7226643 | Thermal pyrolysising chemical vapor deposition method for synthesizing nano-carbon material A thermal cracking chemical vapor deposition method for synthesizing a nano-carbon material is provided. The method includes steps of (a) providing a substrate, (b) spreading a catalyst on the substrate, (c) putting the substrate into a reactor, (d) introducing a ca... | 06/05/2007 |
| 7223654 | MIM capacitor and method of fabricating same A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric... | 05/29/2007 |
| 7221591 | Fabricating bi-directional nonvolatile memory cells A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening se... | 05/22/2007 |
| 7214584 | Method for forming semiconductor device capable of preventing bunker defect Disclosed is a method for preventing a bunker defect generation on a lower portion of a cylinder type metal bottom electrode. The method includes the steps of: forming an etch stop layer on a bottom structure with a conductive region and an insulation region; formin... | 05/08/2007 |
