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| Number | Title | Issue Date |
| RE43326 | Tap connections for circuits with leakage suppression capability An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The l... | 04/24/2012 |
| 7867869 | Laminated thin-film device, manufacturing method thereof, and circuit The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device.... | 01/11/2011 |
| 7838383 | Methods for forming MOS capacitors Method (200) and apparatus (30, 50-53) are described for MOS capacitors (MOS CAPs). The apparatus (30, 50-53) comprises a substrate (31) having Ohmically coupled N and P semiconductor regions (32, 34; 54, 56; 92, 94) ... | 11/23/2010 |
| 7429507 | Semiconductor device having both memory and logic circuit and its manufacture A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the s... | 09/30/2008 |
| 7402890 | Method for symmetric capacitor formation A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first d... | 07/22/2008 |
| 7374992 | Manufacturing method for an integrated semiconductor structure The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device ... | 05/20/2008 |
| 7345355 | Complementary junction-narrowing implants for ultra-shallow junctions Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two spec... | 03/18/2008 |
| 7332401 | Method of fabricating an electrode structure for use in an integrated circuit An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the d... | 02/19/2008 |
| 7314788 | Standard cell back bias architecture An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transist... | 01/01/2008 |
| 7250330 | Method of making an electronic package A method of making an electronic package is described, wherein a substrate is provided with a pattern of conductive pads and a portion of solder positioned on selected ones of the pattern of copper pads. The solder is then reflowed to form partial hemispherically sh... | 07/31/2007 |
| 7247534 | Silicon device on Si:C-OI and SGOI and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second mat... | 07/24/2007 |
| 7223669 | Structure and method for collar self-aligned to buried plate A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench. ... | 05/29/2007 |
| 7190075 | Method of forming smooth polycrystalline silicon electrodes for molecular electronic devices A method is provided for forming smooth polycrystalline silicon electrodes for molecular electronic devices. The method comprises: depositing a silicon layer in an amorphous form; forming a native oxide on a surface of the amorphous silicon layer at a temperature be... | 03/13/2007 |
| 7138321 | Boost capacitor layout technique for an H-bridge integrated circuit motor controller to ensure matching characteristics with that of the low-side switching devices of the bridge An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a low-side driver. A capacitor is coupled to the gate of the low-side dr... | 11/21/2006 |
| 7132346 | Atomic layer deposition of titanium using batch type chamber and method for fabricating capacitor by using the same The present invention relates to a method for fabricating a capacitor employing ALD-TiN as an upper electrode and being suitable for preventing a deterioration of a leakage current property which uses an ALD-TiN as an upper electrode. The method for fabricating the ... | 11/07/2006 |
| 7109545 | Integrated circuit memory with offset capacitor A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern re... | 09/19/2006 |
| 7091085 | Reduced cell-to-cell shorting for memory arrays Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The... | 08/15/2006 |
| 7081385 | Nanotube semiconductor devices and methods for making the same Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cel... | 07/25/2006 |
| 7045416 | Methods of manufacturing ferroelectric capacitors for integrated circuit memory devices Methods of forming integrated circuit capacitors having dielectric layers therein that comprise ferroelectric materials, include the use of protective layers to block the infiltration of hydrogen into the ferroelectric material. By blocking the infiltration of hydro... | 05/16/2006 |
| 7045430 | Atomic layer-deposited LaAlO3 films for gate dielectrics A dielectric film containing LaAlO3 and method of fabricating a dielectric film contained LaAlO3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO2. The LaAlO3 gate di... | 05/16/2006 |
| 6951823 | Plasma ashing process A substantially oxygen-free and nitrogen-free plasma ashing process for removing photoresist in the presence of a low k material from a semiconductor substrate includes forming reactive species by exposing a plasma gas composition to an energy source to form plasma.... | 10/04/2005 |
| 6951826 | Silicon carbide deposition for use as a low dielectric constant anti-reflective coating The present invention generally provides a process for depositing silicon carbide using a silane-based material with certain process parameters that is useful for forming a suitable ARC for IC applications. Under certain process parameters, a fixed thickness of the ... | 10/04/2005 |
| 6940709 | Storage capacitor having a scattering effect and method of manufacturing the same A storage capacitor having a scattering effect is positioned in a substrate for use in a thin film transistor array loop. The storage capacitor is characterized by having a rough layer overlapped by a medium layer and a passivation layer. The storage capacitor furth... | 09/06/2005 |
| 6933590 | Semiconductor device comprising plurality of semiconductor areas having the same top surface and different film thicknesses and manufacturing method for the same A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas i... | 08/23/2005 |
| 6919233 | MIM capacitors and methods for fabricating same Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in ... | 07/19/2005 |
| 6876059 | Semiconductor integrated circuit device and method of manufacturing the same A semiconductor integrated circuit device according to an embodiment of the present invention has an MIM structure capacitor connected between a power source potential electrode wiring and a ground potential electrode wiring each via at least one interlayer connecti... | 04/05/2005 |
| 6867107 | Variable capacitance device and process for manufacturing the same A variable capacitance device comprising, in a semiconductor layer formed on a substrate via an buried oxide film: an n− region 132 formed in the shape of a ring and containing an n-type dopant; an anode 133 adjoined to the outer periphery of the nâˆ... | 03/15/2005 |
| 6808997 | Complementary junction-narrowing implants for ultra-shallow junctions Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two spec... | 10/26/2004 |
| 6787430 | Semiconductor device and method for manufacturing semiconductor device In a semiconductor device and method of manufacturing thereof, a semiconductor device having an SOI structure is provided with a capacitor including a first electrode in an SOI layer, a second electrode opposing the first electrode, and a dielectric film therebetwee... | 09/07/2004 |
| 6777304 | Method for producing an integrated circuit capacitor A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body (17) on a semico... | 08/17/2004 |
| 6767787 | Methods of forming integrated circuits using masks to provide ion implantation shielding to portions of a substrate adjacent to an isolation region therein Methods of forming a channel region between isolation regions of an integrated circuit substrate are disclosed. In particular, a mask can be formed on an isolation region that extends onto a portion of the substrate adjacent to the isolation region to provide a shie... | 07/27/2004 |
| 6762109 | Method of manufacturing semiconductor device with reduced number of process steps for capacitor formation A method of manufacturing a semiconductor device and a method of forming a capacitor allow the formation of a high-performance capacitor without increasing the number of process steps. A silicide protection film (11c) is formed to cover a lower electro... | 07/13/2004 |
| 6753218 | CERAMIC CHIP CAPACITOR OF CONVENTIONAL VOLUME AND EXTERNAL FORM HAVING INCREASED CAPACITANCE FROM USE OF CLOSELY SPACED INTERIOR CONDUCTIVE PLANES RELIABLY CONNECTING TO POSITIONALLY TOLERANT EXTERIOR PADS THROUGH MULTIPLE REDUNDANT VIAS A capacitor including at least one interior metallization plane or plate and a multiplicity of vias for forming multiple redundant electrical connections within the capacitor. Series capacitors are provided having at least two interior plates redundantly electricall... | 06/22/2004 |
| 6704188 | Ultra thin TCS (SiCL4) cell nitride for dram capacitor with DCS (SiH2Cl2) interface seeding layer A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-containing substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-containing gas to desposit a thin silicon... | 03/09/2004 |
| 6670236 | Semiconductor device having capacitance element and method of producing the same To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (2) and the first polycrystalline silicon layer (3) are used as a stress buffering material at the time of formation of the element separation... | 12/30/2003 |
| 6524897 | Semiconductor-on-insulator resistor-capacitor circuit A semiconductor device may be formed with a floating body positioned over an insulator in a semiconductor structure. A gate may be formed over the floating body but spaced therefrom. The semiconductor structure may include doped regions surrounding the fl... | 02/25/2003 |
| 6518070 | Process of forming a semiconductor device and a semiconductor device A process for forming a capacitor with a high-k dielectric or ferroelectric layer within a semiconductor device is used to reduce the likelihood of oxidation or materials interactions between that layer and an underlying layer. A first electrode layer inc... | 02/11/2003 |
| 6498363 | Gapped-plate capacitor In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the... | 12/24/2002 |
| 6495426 | Method for simultaneous formation of integrated capacitor and fuse A process for forming a capacitive structure and a fuse structure in an integrated circuit device includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlyi... | 12/17/2002 |
| 6489196 | Method of forming a capacitor with high capacitance and low voltage coefficient The present invention provides a method of forming a capacitor in an integrated circuit. The method comprises providing a semiconductor substrate having a conductive layer thereon. The partial conductive layer is removed to form an electrode. A plurality ... | 12/03/2002 |
