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| Number | Title | Issue Date |
| 8114753 | Buried decoupling capacitors, devices and systems including same, and methods of fabrication A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried ins... | 02/14/2012 |
| 7915134 | Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capac... | 03/29/2011 |
| 7906405 | Polysilicon structures resistant to laser anneal lightpipe waveguide effects Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, a... | 03/15/2011 |
| 7439127 | Method for fabricating a semiconductor component including a high capacitance per unit area capacitor A method is provided for fabricating a semiconductor component that includes a capacitor having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator ... | 10/21/2008 |
| 7419874 | Method of manufacturing semiconductor device with capacitor and transistor The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor... | 09/02/2008 |
| 7402890 | Method for symmetric capacitor formation A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first d... | 07/22/2008 |
| 7374992 | Manufacturing method for an integrated semiconductor structure The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device ... | 05/20/2008 |
| 7364987 | Method for manufacturing semiconductor device In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-... | 04/29/2008 |
| 7354842 | Methods of forming conductive materials The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to rele... | 04/08/2008 |
| 7332401 | Method of fabricating an electrode structure for use in an integrated circuit An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the d... | 02/19/2008 |
| 7309906 | Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices Improved decoupling capacitor designs and layout schemes are provided that generate high effective capacitance and high area efficiency at higher frequencies than that of previously known decoupling capacitor designs. The improved decoupling capacitor designs utiliz... | 12/18/2007 |
| 7255801 | Deep submicron CMOS compatible suspending inductor A new method is provided for the creation of an inductor. Layers of pad oxide, a thick layer of dielectric and an etch stop layer are successively created over the surface of a substrate. The layers of etch stop material and dielectric are patterned and etched, crea... | 08/14/2007 |
| 7247543 | Decoupling capacitor A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric m... | 07/24/2007 |
| 7223669 | Structure and method for collar self-aligned to buried plate A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench. ... | 05/29/2007 |
| 7115938 | Non-volatile memory cell and method of forming the same A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switchi... | 10/03/2006 |
| 7109090 | Pyramid-shaped capacitor structure A capacitor structure which has a generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first ... | 09/19/2006 |
| 7091083 | Method for producing a capacitor A method for producing a capacitor comprises providing a raw structure having a substrate and at least one dielectric layer, wherein a first area and a second area of the substrate are separated by an isolating layer. Above the first and second areas, an electricall... | 08/15/2006 |
| 7081385 | Nanotube semiconductor devices and methods for making the same Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cel... | 07/25/2006 |
| 7071070 | Method of fabricating capacitor A method of fabricating a capacitor is described. A dielectric layer is formed over a substrate. An upper electrode having multiple openings therein is formed over the dielectric layer. Then, a doping step is performed to the substrate through the openings to form a... | 07/04/2006 |
| 7029983 | Methods of forming MIM type capacitors by forming upper and lower electrode layers in a recess that exposes a source/drain region of a transistor and MIM capacitors so formed A MIM capacitor can be formed by forming an insulating layer on a source/drain region of a transistor. A first pattern is formed on the insulating layer. A recess is formed in the insulating layer using the first pattern, wherein the recess exposes the source/drain ... | 04/18/2006 |
| 7029971 | Thin film dielectrics for capacitors and methods of making thereof Dielectrics are formed having high dielectric constants, low loss tangents, and other desirable electrical and physical properties. The dielectrics are annealed at temperatures allowing the use of copper foil substrates, and at low oxygen partial pressures. ... | 04/18/2006 |
| 6992939 | Method and apparatus for identifying short circuits in an integrated circuit device The disclosed embodiments relate to a method and apparatus for identifying short circuits in an integrated circuit device. The method may comprise the acts of programming a first memory cell associated with a first digit line to a first data value, programming a sec... | 01/31/2006 |
| 6979624 | Reduced mask count buried layer process An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of t... | 12/27/2005 |
| 6956261 | Semiconductor device and method for manufacturing the same A first DRAM section including a first memory cell having a first capacitance and a second DRAM section including a second memory cell having a second capacitance different from the first capacitance are provided on the same semiconductor substrate. ... | 10/18/2005 |
| 6949442 | Methods of forming MIM capacitors A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bott... | 09/27/2005 |
| 6927442 | Charge pump device A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and ... | 08/09/2005 |
| 6919233 | MIM capacitors and methods for fabricating same Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in ... | 07/19/2005 |
| 6876059 | Semiconductor integrated circuit device and method of manufacturing the same A semiconductor integrated circuit device according to an embodiment of the present invention has an MIM structure capacitor connected between a power source potential electrode wiring and a ground potential electrode wiring each via at least one interlayer connecti... | 04/05/2005 |
| 6867107 | Variable capacitance device and process for manufacturing the same A variable capacitance device comprising, in a semiconductor layer formed on a substrate via an buried oxide film: an n− region 132 formed in the shape of a ring and containing an n-type dopant; an anode 133 adjoined to the outer periphery of the nâˆ... | 03/15/2005 |
| 6858513 | Method for manufacturing a semiconductor device with MIS capacitors with dielectric film in common A semiconductor device having an MIS capacitor having a low capacitance value and an MIS capacitor having a high capacitance value formed on the same substrate, and a manufacturing method thereof. The first MIS capacitor consists of a lower conductive material regio... | 02/22/2005 |
| 6777304 | Method for producing an integrated circuit capacitor A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body (17) on a semico... | 08/17/2004 |
| 6773981 | Methods of forming capacitors Capacitors and methods of forming capacitors are disclosed. In one implementation, a capacitor comprises a capacitor dielectric layer comprising Ta2O5 formed over a first capacitor electrode. A second capacitor electrode is formed over the Ta | 08/10/2004 |
| 6770525 | Method of fabricating capacitors for semiconductor devices Disclosed is a method for fabricating capacitors for semiconductor devices. This method includes the steps of forming a lower electrode on an understructure of a semiconductor substrate, depositing an amorphous TaON thin film over the lower electrode, annealing the ... | 08/03/2004 |
| 6762109 | Method of manufacturing semiconductor device with reduced number of process steps for capacitor formation A method of manufacturing a semiconductor device and a method of forming a capacitor allow the formation of a high-performance capacitor without increasing the number of process steps. A silicide protection film (11c) is formed to cover a lower electro... | 07/13/2004 |
| 6677215 | Method of fabricating a diode protecting a gate electrode of a field effect transistor There is provided a method including the steps of: forming spaced gate patterns on a main surface of a semiconductor substrate; forming sidewall films on the gate patterns, respectively, at their respective sidewalls facing each other; and, with the gate ... | 01/13/2004 |
| 6670236 | Semiconductor device having capacitance element and method of producing the same To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (2) and the first polycrystalline silicon layer (3) are used as a stress buffering material at the time of formation of the element separation... | 12/30/2003 |
| 6538271 | Semiconductor device and method of manufacturing the same A semiconductor device comprises a semiconductor substrate and a silicon nitride film formed on the semiconductor substrate. The silicon nitride film is substantially free from an Si--H bond and has an Si--H density per unit area of 1×1015 cm | 03/25/2003 |
| 6524897 | Semiconductor-on-insulator resistor-capacitor circuit A semiconductor device may be formed with a floating body positioned over an insulator in a semiconductor structure. A gate may be formed over the floating body but spaced therefrom. The semiconductor structure may include doped regions surrounding the fl... | 02/25/2003 |
| 6498714 | Thin film capacitance device and printed circuit board The present invention relates to a thin film capacitor device having a copper wiring layer, a dielectric layer, and a barrier layer interposed between the wiring layer and the dielectric layer. The barrier layer has the function of preventing diffusion of... | 12/24/2002 |
| 6495426 | Method for simultaneous formation of integrated capacitor and fuse A process for forming a capacitive structure and a fuse structure in an integrated circuit device includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlyi... | 12/17/2002 |
