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| Number | Title | Issue Date |
| 7888228 | Method of manufacturing an integrated circuit, an integrated circuit, and a memory module According to one embodiment of the present invention, a method of manufacturing an integrated circuit including a memory device includes, generating a solid electrolyte layer including a first solid electrolyte layer area and a second solid electrolyte layer area, t... | 02/15/2011 |
| 7550359 | Methods involving silicon-on-insulator trench memory with implanted plate A method for fabricating silicon-on-insulator (SOI) trench memory includes forming a trench on a substrate, wherein a buried oxide layer is disposed on the substrate, a SOI layer is disposed on the buried oxide layer, and a hardmask layer is disposed on the SOI laye... | 06/23/2009 |
| 7419872 | Method for preparing a trench capacitor structure A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer su... | 09/02/2008 |
| 7410862 | Trench capacitor and method for fabricating the same A trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The method of fabricating the trench capacitor includes the steps of forming a trench in the semic... | 08/12/2008 |
| 7368341 | Semiconductor circuit arrangement with trench isolation and fabrication method An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insula... | 05/06/2008 |
| 7354523 | Methods for sidewall etching and etching during filling of a trench A method for sidewall etching includes providing a substrate having a trench defined therein, with the trench having fill material disposed over a bottom thereof, along a sidewall thereof, and at the trench opening. The fill material along the sidewall of the trench... | 04/08/2008 |
| 7332401 | Method of fabricating an electrode structure for use in an integrated circuit An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the d... | 02/19/2008 |
| 7332412 | Structure of strained silicon on insulator and method of manufacturing the same Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO | 02/19/2008 |
| 7326523 | Low refractive index polymers as underlayers for silicon-containing photoresists A new underlayer composition that exhibits high etch resistance and improved optical properties is disclosed. The underlayer composition comprises a vinyl or acrylate polymer, such as a methacrylate polymer, the polymer comprising at least one substituted or unsubst... | 02/05/2008 |
| 7294554 | Method to eliminate arsenic contamination in trench capacitors A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also pr... | 11/13/2007 |
| 7294543 | DRAM (Dynamic Random Access Memory) cells A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semicon... | 11/13/2007 |
| 7291565 | Method and system for treating a substrate with a high pressure fluid using fluorosilicic acid A method and system is described for treating a substrate with a high pressure fluid, such as carbon dioxide in a supercritical state. A process chemistry is introduced to the high pressure fluid for treating the substrate surface. The process chemistry comprises fl... | 11/06/2007 |
| 7265058 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device comprises, in patterning of a conductive film having a grain boundary on a very thin dielectric film, a first etching step of carrying out anisotropic etching until most of the conductive film in a flat portion disapp... | 09/04/2007 |
| 7250374 | System and method for processing a substrate using supercritical carbon dioxide processing A method and system for processing a substrate in a film removal system. The method includes providing the substrate in a substrate chamber of a film removal system, where the substrate has a micro-feature containing a dielectric film on a sidewall of the micro-feat... | 07/31/2007 |
| 7232718 | Method for forming a deep trench capacitor buried plate A method for forming a deep trench capacitor buried plate. A substrate having a pad oxide and a pad nitride is provided. A deep trench is formed in the substrate. A doped silicate film is deposited on a sidewall of the deep trench. A sacrificial layer is deposited i... | 06/19/2007 |
| 7223653 | Process for forming a buried plate A method is provided for making a buried plate region in a semiconductor substrate. According to such method, a trench is formed in a semiconductor substrate, the trench having a trench sidewall, the sidewall including an upper portion, and a lower portion disposed ... | 05/29/2007 |
| 7157328 | Selective etching to increase trench surface area The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is int... | 01/02/2007 |
| 7094658 | 3-stage method for forming deep trench structure and deep trench capacitor A method for forming a deep trench structure comprises the steps of providing a silicon substrate; forming a mask layer of a predetermined pattern on the silicon substrate to expose a portion of the silicon substrate; forming a first trench in the exposed portion of... | 08/22/2006 |
| 7094659 | Method of forming deep trench capacitors A method of forming a trench capacitor is disclosed. After completion of the bottom electrode of the capacitor, a collar dielectric layer is directly formed on the sidewall of the deep trench using self-starved atomic layer chemical vapor deposition (self-starved AL... | 08/22/2006 |
| 7081385 | Nanotube semiconductor devices and methods for making the same Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cel... | 07/25/2006 |
| 7078291 | Method for fabricating a deep trench capacitor This invention pertains to a method for making a trench capacitor of DRAM devices. A single-sided spacer is situated on the sidewall of a recess at the top of the trench capacitor prior to the third polysilicon deposition and recess etching process. The single-sided... | 07/18/2006 |
| 7057231 | Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate A floating gate (110) of a nonvolatile memory cell is formed in a trench (114) in a semiconductor substrate (220). A dielectric (128) covers the surface of the trench. The wordline (140) has a portion overlying the trench. The cell... | 06/06/2006 |
| 7022623 | Method of fabricating a semiconductor device with a dielectric film using a wet oxidation with steam process A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrat... | 04/04/2006 |
| 7011923 | Negative photoresist and method of using thereof A negative photoresist composition and a method of patterning a substrate through use of the negative photoresist composition. The negative photoresist composition comprises a radiation sensitive acid generator, a first polymer containing an alkoxymethyl amido group... | 03/14/2006 |
| 6969648 | Method for forming buried plate of trench capacitor A method for forming a buried plate in a trench capacitor is disclosed. The trench is completely filled with a dopant source material such as ASG. The dopant source material is then recessed and the collar material is deposited to form the collar in the upper portio... | 11/29/2005 |
| 6962847 | Method for forming a self-aligned buried strap in a vertical memory cell A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The colla... | 11/08/2005 |
| 6946345 | Self-aligned buried strap process using doped HDP oxide The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conduct... | 09/20/2005 |
| 6946344 | Method for forming trench capacitor A method for forming a trench capacitor. A semiconductor substrate with a trench is provided, and a trench capacitor is formed in the trench with a storage node and a node dielectric layer. The top portion of the trench is ion implanted to a predetermined angle to f... | 09/20/2005 |
| 6930012 | Semiconductor memory with trench capacitor and method of manufacturing the same A semiconductor memory device includes first and second semiconductor layers, a buried insulating layer, a trench comprising a retreated portion, and the trench defining a first opening width at the second semiconductor layer, a first capacitor electrode formed in t... | 08/16/2005 |
| 6927123 | Method for forming a self-aligned buried strap in a vertical memory cell A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and th... | 08/09/2005 |
| 6924204 | Split gate flash memory cell and manufacturing method thereof A method for fabricating a buried plate of a deep trench capacitor is described. A substrate having a deep trench therein is provided. A doped layer is formed on the surface of the deep trench and a material layer is formed on the doped layer. A passivation layer is... | 08/02/2005 |
| 6916703 | Method for forming uniform bottom electrode in trench of trench capacitor A method for forming a uniform bottom electrode in a trench of a trench capacitor. A semiconductor substrate has a dense trench area and a less dense trench area with a plurality of trenches formed in both areas respectively. A hard mask layer is formed on the semic... | 07/12/2005 |
| 6902982 | Trench capacitor and process for preventing parasitic leakage A trench capacitor process for preventing parasitic leakage. The process is capable of blocking leakage current from a parasitic transistor adjacent to the trench, and includes the steps of forming a doping layer and a cap layer covering portions of the sidewall of ... | 06/07/2005 |
| 6881620 | Method of fabricating deep trench capacitor A method of fabricating a deep trench capacitor is provided. A substrate with a deep trench thereon is provided. A bottom electrode is formed at a bottom of the deep trench and a capacitor dielectric layer, a first conductive layer, a protective layer and a collar l... | 04/19/2005 |
| 6878600 | Method for fabricating trench capacitors and semiconductor device with trench capacitors A method for fabricating trench capacitors having trenches with mesopores, the trench capacitors being suitable both for discrete capacitors and for integrated semiconductor memories, significantly increases the surface area for electrodes of the capacitors and, hen... | 04/12/2005 |
| 6875653 | DRAM cell structure with buried surrounding capacitor and process for manufacturing the same A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and... | 04/05/2005 |
| 6872621 | Method for removal of hemispherical grained silicon in a deep trench A method for removal of hemispherical grained silicon (HSG) in a deep trench is described. A buried silicon germanium (SiGe) layer serving as an etch stop layer is formed in the collar region of the trench, followed by depositing a HSG layer. The HSG layer is then s... | 03/29/2005 |
| 6849496 | DRAM with vertical transistor and trench capacitor memory cells and method of fabrication A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the ac... | 02/01/2005 |
| 6808979 | Method for forming vertical transistor and trench capacitor A method for forming a vertical transistor and a trench capacitor. A semiconductor substrate having a pad stacked layer on the surface and a trench formed therein is provided. A capacitor is formed at the bottom part of the trench and a portion of the upper sidewall... | 10/26/2004 |
| 6797582 | Vertical thermal nitride mask (anti-collar) and processing thereof A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of eac... | 09/28/2004 |
