Class 438/391 - Including isolation means formed in trench

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a trench capacitor having structure functioning
No. of patents: 131
Last issue date: 12/28/2010

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Number	Title	Issue Date
7858485	Structure and method for manufacturing trench capacitance A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so ...	12/28/2010
7709342	Capacitor and method of manufacturing the same A capacitor and method of manufacturing the same include an insulating interlayer, a lower electrode, a protection structure, a dielectric layer and an upper electrode. The insulating interlayer may include a conductive pattern formed on a substrate. The lower elect...	05/04/2010
7416952	Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal n...	08/26/2008
7416937	Semiconductor device and method for fabricating the same A method creates semiconductor device in which a storage dielectric film and a storage electrode included in the capacitor is transferred from an inactive region of a semiconductor substrate to the active region thereof, i.e., into a device isolating trench such tha...	08/26/2008
7410862	Trench capacitor and method for fabricating the same A trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The method of fabricating the trench capacitor includes the steps of forming a trench in the semic...	08/12/2008
7402889	Semiconductor device and method for manufacturing the same Disclosed is a metal-insulator-metal (MIM) capacitor structure formed by a metal interconnection process of trench-exposed metal layers formed on stacked interlayer insulating layers. The MIM capacitor uses a conductive layer conformally formed on the metal intercon...	07/22/2008
7393750	Method for manufacturing a semiconductor device Embodiments relate to a method of manufacturing a semiconductor device. According to embodiments, the method may include forming a first and a second insulating layer on a semiconductor substrate of which an active area and an isolation region are defined, forming a...	07/01/2008
7390717	Trench power MOSFET fabrication using inside/outside spacers A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are for...	06/24/2008
7358145	Method of fabricating shallow trench isolation structure A method of fabricating a shallow trench isolation structure is provided. A substrate is provided with a pad layer, a mask layer and a shallow trench formed therein. A liner oxide layer is formed on the sidewall of the shallow trench and then a silicon nitride layer...	04/15/2008
7354812	Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre...	04/08/2008
7344949	Non-volatile memory device and method of fabricating the same A method of fabricating an a non-volatile memory includes forming trench isolation regions in an inactive region of a semiconductor substrate, adjacent trench isolation regions defining respective protrusions having rounded edges therebetween, wherein upper surfaces...	03/18/2008
7344953	Process for vertically patterning substrates in semiconductor process technology by means of inconformal deposition On a substrate surface, which has been patterned in the form of a relief, of a substrate, typically of a semiconductor wafer, a deposition process is used to provide a covering layer on process surfaces which are vertical or inclined with respect to the substrate su...	03/18/2008
7342276	Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme...	03/11/2008
7338850	Method for manufacturing device isolation film of semiconductor device A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to pr...	03/04/2008
7303953	Production of an integrated capacitor A process for producing a capacitor integrated into an electronic circuit comprises the formation of a trench in a substrate through a conductive portion similar to an MOS transistor gate. Alternating conductive, insulating and conductive layers are deposited inside...	12/04/2007
7273790	Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected th...	09/25/2007
7268028	Well isolation trenches (WIT) for CMOS devices A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical ...	09/11/2007
7262089	Methods of forming semiconductor structures The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for ex...	08/28/2007
7262090	Random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes A process for fabricating a novel random access memory (RAM) capacitor in a shallow trench isolation (STI) The method utilizes a novel node photoresist mask for plasma etching recesses in the STI that prevents plasma-etch-induced defects in the substrate. This novel...	08/28/2007
7229887	Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby The invention relates to a phase-change memory device. The device includes a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase-change memory mate...	06/12/2007
7223651	Dram memory cell with a trench capacitor and method for production thereof A memory cell includes a selection transistor and a trench capacitor. The trench capacitor is filled with a conductive trench filling on which an insulating covering layer is arranged. The insulating covering layer is laterally overgrown, proceeding from the substra...	05/29/2007
7223669	Structure and method for collar self-aligned to buried plate A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench. ...	05/29/2007
7214957	PRAMS having phase-change layer pattern with electrode contact area and methods of forming the same According to some embodiments of the present invention, there are provided PRAMS having a phase-change layer pattern interposed between a molding layer and a forming layer pattern, and methods of forming the same that include a node conductive layer pattern, a moldi...	05/08/2007
7163857	Buried strap contact for a storage capacitor and method for fabricating it A buried strap contact between a trench capacitor of a memory cell and the subsequently formed selection transistor of the memory cell is fabricated such that the inner capacitor electrode layer is etched back in the trench of the trench capacitor and the uncovered ...	01/16/2007
7157328	Selective etching to increase trench surface area The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is int...	01/02/2007
7153781	Method to etch poly Si gate stacks with raised STI structure In a process for etching poly Si gate stacks with raised STI structure where the thickness of poly Si gates at the AA and STI are different, the improvement comprising: a) etching a gate silicide layer+a poly Si 2 layer; ...	12/26/2006
7153738	Method for making a trench memory cell A process is provided for forming a trench capacitor, such as used in a DRAM memory cell, in which the required number of polysilicon deposition steps and planarization steps are reduced. A first region of a first material is formed in the bottom portion of the tren...	12/26/2006
7153737	Self-aligned, silicided, trench-based, DRAM/EDRAM processes with improved retention A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending be...	12/26/2006
7125496	Etching method using photoresist etch barrier A method of etching is disclosed using a photoresist etch barrier formed by an exposure with a light source of which wavelength is in the range of 157 nm to 193 nm, such as an argon fluoride(ArF) laser or fluorine laser(F2 laser), the method includes the ...	10/24/2006
7122439	Method of fabricating a bottle trench and a bottle trench capacitor A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substr...	10/17/2006
7098102	Shallow trench isolation structure and dynamic random access memory, and fabricating methods thereof A method for fabricating a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate. An ion implantation is performed to form a doped region in a predetermined depth in the substrate exposed by the mask layer. An etching...	08/29/2006
7091089	Method of forming a nanocluster charge storage device In one embodiment, a method of forming a nanocluster charge storage device is provided. A first region of a semiconductor device is identified for locating one or more non-charge storage devices. A second region of the semiconductor device is identified for locating...	08/15/2006
7081385	Nanotube semiconductor devices and methods for making the same Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cel...	07/25/2006
7081384	Method of forming a silicon dioxide layer The present invention refers to a method of forming a silicon dioxide layer by thermally oxidizing at least one monocrystalline silicon surface region on a semiconductor substrate. The silicon surface region has a curved surface. The method can include providing a s...	07/25/2006
7078291	Method for fabricating a deep trench capacitor This invention pertains to a method for making a trench capacitor of DRAM devices. A single-sided spacer is situated on the sidewall of a recess at the top of the trench capacitor prior to the third polysilicon deposition and recess etching process. The single-sided...	07/18/2006
7078290	Method for forming a top oxide with nitride liner A method for forming a top oxide for a deep trench memory device comprising a poly stud above a polysilicon fill in a deep trench and an isolation region in a portion of the deep trench, comprises forming an etch support nitride liner by low-pressure chemical vapor ...	07/18/2006
7049202	Method of manufacturing semiconductor device A method of manufacturing a lateral trench-type MOSFET exhibiting a high breakdown voltage and including an offset drain region around a trench. Specifically, impurity ions are irradiated obliquely to the side wall of a trench to implant the impurity ions only into ...	05/23/2006
7033896	Field effect transistor with a high breakdown voltage and method of manufacturing the same An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the ...	04/25/2006
7022565	Method of fabricating a trench capacitor of a mixed mode integrated circuit A method of fabricating a trench capacitor of a mixed mode integrated circuit includes forming shallow trench isolation regions for isolating active/passive devices on a semiconductor substrate. The lower electrode layer of the polysilicon layer, the dielectric laye...	04/04/2006
7015090	Method of manufacturing a semiconductor device having trenches for isolation and capacitor formation trenches At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor per unit are...	03/21/2006

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Class 438/391 - Including isolation means formed in trench