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| Number | Title | Issue Date |
| 7419883 | Method for fabricating a semiconductor structure having selective dopant regions A method for fabricating a semiconductor structure having selective dopant regions in a semiconductor substrate having trenches formed therein I disclosed. In one embodiment, by a dopant source of an auxiliary structure, parts of the semiconductor structure which li... | 09/02/2008 |
| 7416952 | Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal n... | 08/26/2008 |
| 7345355 | Complementary junction-narrowing implants for ultra-shallow junctions Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two spec... | 03/18/2008 |
| 7335538 | Method for manufacturing bottom substrate of liquid crystal display device A method for manufacturing liquid crystal display substrates comprises the steps of: (a) providing a substrate having a transparent electrode layer and a metal layer; (b) forming a patterned photoresist layer through half-tone or diffraction; (c) defining signal lin... | 02/26/2008 |
| 7166890 | Superjunction device with improved ruggedness An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through t... | 01/23/2007 |
| 7157328 | Selective etching to increase trench surface area The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is int... | 01/02/2007 |
| 7115524 | Methods of processing a semiconductor substrate The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A la... | 10/03/2006 |
| 7094658 | 3-stage method for forming deep trench structure and deep trench capacitor A method for forming a deep trench structure comprises the steps of providing a silicon substrate; forming a mask layer of a predetermined pattern on the silicon substrate to expose a portion of the silicon substrate; forming a first trench in the exposed portion of... | 08/22/2006 |
| 7091059 | Method of forming a photosensor comprising a plurality of trenches A method of forming a multiple-trench photosensor for use in a CMOS imager having an improved charge capacity. The multi-trench photosensor may be either a photogate or photodiode structure. The multi-trench photosensor provides the photosensitive element with an in... | 08/15/2006 |
| 7049202 | Method of manufacturing semiconductor device A method of manufacturing a lateral trench-type MOSFET exhibiting a high breakdown voltage and including an offset drain region around a trench. Specifically, impurity ions are irradiated obliquely to the side wall of a trench to implant the impurity ions only into ... | 05/23/2006 |
| 7033885 | Deep trench structure manufacturing process Disclosed is a method for manufacturing deep trench structure comprising the steps of providing a substrate; forming a deep trench in the substrate; forming a nitride layer in the deep trench; filling the deep trench with a first conductive layer; removing a portion... | 04/25/2006 |
| 6989312 | Method for fabricating semiconductor optical device Provided is a method for fabricating a semiconductor optical device that can be used as a reflecting semiconductor mirror or an optical filter, in which two or more types of semiconductor layers having different etch rates are alternately stacked, at least one type ... | 01/24/2006 |
| 6962847 | Method for forming a self-aligned buried strap in a vertical memory cell A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The colla... | 11/08/2005 |
| 6953725 | Method for fabricating memory device having a deep trench capacitor A method of fabricating a memory device having a deep trench capacitor is described. A first conductive layer is formed in the lower and middle portions of a deep trench in a substrate. An undoped semiconductor layer is formed in the upper portion of the deep trench... | 10/11/2005 |
| 6946344 | Method for forming trench capacitor A method for forming a trench capacitor. A semiconductor substrate with a trench is provided, and a trench capacitor is formed in the trench with a storage node and a node dielectric layer. The top portion of the trench is ion implanted to a predetermined angle to f... | 09/20/2005 |
| 6939723 | Method of forming haze-free BST films Described herein is a method for producing a haze-free (Ba, Sr)TiO3 (BST) film, and devices incorporating the same. In one embodiment, the BST film is made haze-free by depositing the film with a substantially uniform desired crystal orientation, for exam... | 09/06/2005 |
| 6927123 | Method for forming a self-aligned buried strap in a vertical memory cell A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and th... | 08/09/2005 |
| 6927124 | Method of manufacturing semiconductor device In a method of manufacturing a capacitor, a semiconductor substrate is provided. On the semiconductor substrate, a transistor is formed. Then, a first conductive layer is formed on the substrate. An insulating layer is formed on the first conductive layer. A second ... | 08/09/2005 |
| 6927430 | Shared bit line cross-point memory array incorporating P/N junctions A shared bit line cross-point memory array structure is provided, along with methods of manufacture. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the ... | 08/09/2005 |
| 6887768 | Method and structure for composite trench fill A method and structure for a composite trench fill for silicon electronic devices. On a planar silicon substrate having a first deposited layer of oxide and a second deposited layer of polysilicon, a trench is etched. Deposition and etch processes using a combinatio... | 05/03/2005 |
| 6878603 | Process for manufacturing a DMOS transistor In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially... | 04/12/2005 |
| 6828191 | Trench capacitor with an insulation collar and method for producing a trench capacitor A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielect... | 12/07/2004 |
| 6825058 | Methods of fabricating trench isolated cross-point memory array Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the r... | 11/30/2004 |
| 6808997 | Complementary junction-narrowing implants for ultra-shallow junctions Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two spec... | 10/26/2004 |
| 6602749 | Capacitor under bitline (CUB) memory cell structure with reduced parasitic capacitance Within a method for forming a memory cell structure there is provided a field effect transistor (FET) device having electrically connected to one of its source/drain regions a storage capacitor and electrically connected to the other of its source/drain r... | 08/05/2003 |
| 6500707 | Method for manufacturing a trench capacitor of a memory cell of a semiconductor memory A trench is formed in a substrate with an upper region and a lower region. The trench is subsequently widened in its upper region and in its lower region by isotropic etching. In the upper region, an insulating collar is formed that is designated as a bur... | 12/31/2002 |
| 6444575 | Method for forming a bitline contact via within a memory cell structure Within a method for forming a contact via there is provided a substrate having formed thereover a pair of topographic structures separated by a contact region formed within the substrate. There is then formed upon the substrate and the pair of topographic... | 09/03/2002 |
| 6399435 | Method for producing a DRAM cell with a trench capacitor The present invention provides a method for fabricating a DRAM cell having a trench capacitor. In order to simplify the fabrication method for a DRAM cell, to ensure a high yield and to achieve a high packing density of the DRAM cells, the invention propo... | 06/04/2002 |
| 6372573 | Self-aligned trench capacitor capping process for high density DRAM cells A process for eliminating roughness on a silicon nitride trench liner is disclosed. A capping film on the top of the trench is formed in a self-aligned manner. This capping film prevents short circuits between a storage node and a passing word-line.... | 04/16/2002 |
| 6362040 | Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the a... | 03/26/2002 |
| 6352866 | Method for improving the sidewall stoichiometry of thin film capacitors A method for ion implantation of high dielectric constant materials with dopants to improve sidewall stoichiometry is disclosed. Particularly, the invention relates to ion implantation of (Ba,Sr)TiO3 (BST) with Ti dopants. The invention also re... | 03/05/2002 |
| 6284593 | Method for shallow trench isolated, contacted well, vertical MOSFET DRAM A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects is provided.... | 09/04/2001 |
| 6261894 | Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays Methods of preparing dual workfunction high-performance support metal oxide semiconductor field effect transistor (MOSFETs)/embedded dynamic random access (EDRAM) arrays are provided. The methods describe herein reduce the number of deep-UV masks used in ... | 07/17/2001 |
| 6245612 | Method for making the bottom electrode of a capacitor The present invention provides a method for making the bottom electrode of a buried capacitor, which is characterized by protecting the non-bottom electrode region with a LPD oxide layer to prevent the impurities within the doped Si glass remaining in non... | 06/12/2001 |
| 6232171 | Technique of bottle-shaped deep trench formation A method for fabricating deep-submicron vertically arranged capacitors is disclosed which allows the capacitor to enjoy an enhanced sidewall surface so as to attain a capacitance of 40 pF or more. The method comprises the steps of: (a) forming an elongate... | 05/15/2001 |
| 6211006 | Method of forming a trench-type capacitor The present invention relates to a method of forming a trench-type capacitor. More particularly, the plate areas of the trench-type capacitor are increased according to the present invention. The method of this invention comprises the steps of: providing ... | 04/03/2001 |
| 6207494 | Isolation collar nitride liner for DRAM process improvement A method of fabricating a trench cell capacitor can be used in the formation of a DRAM cell. In one embodiment, a trench is formed within a semiconductor substrate. The trench is lined with a dielectric layer, e.g., an ONO layer. After lining the trench, ... | 03/27/2001 |
| 6190971 | Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region A method and structure for manufacturing an integrated circuit device includes forming a storage device in a substrate, lithographically forming a gate opening in the substrate over the storage device, forming first spacers in the gate opening, forming a ... | 02/20/2001 |
| 6180451 | Method of forming capacitor with a HSG layer A method of forming a DRAM capacitor. A hemispherical grain structure is formed on the surface of the bottom electrode of the capacitor. By employing an additional annealing under a dopant contained ambient, the dopant is diffused into the hemispherical g... | 01/30/2001 |
| 6133091 | Method of fabricating a lower electrode of capacitor A method of fabricating a lower electrode of a capacitor. A sacrificial multilayer is formed on a semiconductor layer. The sacrificial multi-layer is a stack of alternating first and second sacrificial layers. A patterned first mask layer having a first o... | 10/17/2000 |
