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| Number | Title | Issue Date |
| 8008160 | Method and structure for forming trench DRAM with asymmetric strap A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric ... | 08/30/2011 |
| 7919385 | Semiconductor device and method of forming the same A semiconductor device includes a first insulating layer, a capacitor, an adhesive layer, and an intermediate layer. The first insulating layer may include a first insulating film. The first insulating layered structure has a first hole. The capacitor is disposed in... | 04/05/2011 |
| 7883984 | Method of manufacturing flash memory device A method of manufacturing a flash memory device may include forming a trench, defining at least a common source region, on a semiconductor substrate, forming a gate poly over the semiconductor substrate, performing an ion implantation process employing a first photo... | 02/08/2011 |
| 7709341 | Methods of shaping vertical single crystal silicon walls and resulting structures A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the ... | 05/04/2010 |
| 7662694 | Capacitor having adjustable capacitance, and printed wiring board having the same The capacitance of a capacitor is adjusted by forming openings in one of a pair of electrodes of the capacitor, the openings having different sizes d1, d2, d3, . . . , wherein d1>d2>d3> . . . and being arranged in numbers n | 02/16/2010 |
| 7439150 | Method of manufacturing a semiconductor device In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the firs... | 10/21/2008 |
| 7439151 | Method and structure for integrating MIM capacitors within dual damascene processing techniques A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer h... | 10/21/2008 |
| 7410862 | Trench capacitor and method for fabricating the same A trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The method of fabricating the trench capacitor includes the steps of forming a trench in the semic... | 08/12/2008 |
| 7410891 | Method of manufacturing a superjunction device A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etche... | 08/12/2008 |
| 7390713 | Method for forming trench memory cell structures for DRAMS One embodiment of the invention relates to a method for forming trench memory cell structures having trench capacitors and planar selection transistors. An implantation for forming a reinforcement implant for improving the electrical connection of a storage electrod... | 06/24/2008 |
| 7358149 | Substrate isolation in integrated circuits Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transis... | 04/15/2008 |
| 7354821 | Methods of fabricating trench capacitors with insulating layer collars in undercut regions Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the firs... | 04/08/2008 |
| 7335968 | High permeability composite films to reduce noise in high speed interconnects A transmission line circuit provides a structure for improved transmission line operation on integrated circuits. The transmission line circuit includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed ... | 02/26/2008 |
| 7326612 | Method for fabricating a semiconductor structure A method is provided for fabricating a semiconductor structure, such as a DRAM memory cell, that includes an elevated region with at least one sidewall. The at least one sidewall is provided with an insulation layer. A mask layer is applied to the insulation layer. ... | 02/05/2008 |
| 7327016 | High permeability composite films to reduce noise in high speed interconnects An electronic system is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating ma... | 02/05/2008 |
| 7294554 | Method to eliminate arsenic contamination in trench capacitors A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also pr... | 11/13/2007 |
| 7294901 | Semiconductor device with improved resurf features including trench isolation structure A p impurity region (3) defines a RESURF isolation region in an n− semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n− | 11/13/2007 |
| 7244649 | Method of manufacturing a capacitor having improved capacitance and method of manufacturing a semiconductor device including the capacitor A method for manufacturing a capacitor is disclosed. An etch-stop layer or a polishing stop layer is employed to protect a storage electrode of the capacitor from being damaged by a chemical mechanical polishing process or an etch-back process during its fabrication... | 07/17/2007 |
| 7242058 | Lateral semiconductor device using trench structure and method of manufacturing the same A semiconductor device has a semiconductor substrate and a trench region having at least one trench disposed on a surface of the semiconductor substrate and having a trench length, a trench width and a trench depth. A well region is disposed in the substrate and sur... | 07/10/2007 |
| 7235457 | High permeability layered films to reduce noise in high speed interconnects This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conduc... | 06/26/2007 |
| 7223651 | Dram memory cell with a trench capacitor and method for production thereof A memory cell includes a selection transistor and a trench capacitor. The trench capacitor is filled with a conductive trench filling on which an insulating covering layer is arranged. The insulating covering layer is laterally overgrown, proceeding from the substra... | 05/29/2007 |
| 7223669 | Structure and method for collar self-aligned to buried plate A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench. ... | 05/29/2007 |
| 7224027 | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an e... | 05/29/2007 |
| 7199006 | Planarization method of manufacturing a superjunction device A method of manufacturing a semiconductor device includes providing a substrate having first and second main surfaces. The substrate has a heavily doped region of a first conductivity at the second main surface and has a lightly doped region of the first conductivit... | 04/03/2007 |
| 7183217 | Dry-etching method A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas co... | 02/27/2007 |
| 7157328 | Selective etching to increase trench surface area The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is int... | 01/02/2007 |
| 7153737 | Self-aligned, silicided, trench-based, DRAM/EDRAM processes with improved retention A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending be... | 12/26/2006 |
| 7148117 | Methods for forming shallow trench isolation structures in semiconductor devices Methods for forming STI structures in semiconductor devices are disclosed. A disclosed method comprises: forming a buffer oxide layer on a silicon substrate; implanting ions into the entire surface of the resulting structure and removing the buffer oxide layer; depo... | 12/12/2006 |
| 7122439 | Method of fabricating a bottle trench and a bottle trench capacitor A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substr... | 10/17/2006 |
| 7118956 | Trench capacitor and a method for manufacturing the same A trench capacitor comprises a semiconductor substrate, a trench, formed in the semiconductor substrate, having upper and lower portions, a first doped polysilicon layer filled in the lower portion through a first dielectric film and doped with a first impurity havi... | 10/10/2006 |
| 7118998 | Method of forming a conductive structure A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bott... | 10/10/2006 |
| 7112506 | Method for forming capacitor of semiconductor device Disclosed is a method for forming a capacitor of a semiconductor device. An etch stop layer, first oxide layer and second oxide layer are sequentially deposited on an insulating interlayer of a substrate. Contact holes through which portions of the etch stop layer a... | 09/26/2006 |
| 7101770 | Capacitive techniques to reduce noise in high speed interconnections Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The present invention offers an improved signal to noise ration. The present invention provides for the fabr... | 09/05/2006 |
| 7098102 | Shallow trench isolation structure and dynamic random access memory, and fabricating methods thereof A method for fabricating a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate. An ion implantation is performed to form a doped region in a predetermined depth in the substrate exposed by the mask layer. An etching... | 08/29/2006 |
| 7094658 | 3-stage method for forming deep trench structure and deep trench capacitor A method for forming a deep trench structure comprises the steps of providing a silicon substrate; forming a mask layer of a predetermined pattern on the silicon substrate to expose a portion of the silicon substrate; forming a first trench in the exposed portion of... | 08/22/2006 |
| 7078291 | Method for fabricating a deep trench capacitor This invention pertains to a method for making a trench capacitor of DRAM devices. A single-sided spacer is situated on the sidewall of a recess at the top of the trench capacitor prior to the third polysilicon deposition and recess etching process. The single-sided... | 07/18/2006 |
| 7078307 | Method for manufacturing single-sided buried strap in semiconductor devices A method for manufacturing a single-ended buried strap used in semiconductor devices is disclosed. According to the present invention, a trench capacitor structure is formed in a semiconductor substrate, wherein the trench capacitor structure has a contact surface l... | 07/18/2006 |
| 7067874 | Semiconductor device including trench with at least one of an edge of an opening and a bottom surface being round A semiconductor device that includes an insulating substrate, a plurality of semiconductor layers arranged to be isolated from one another on the insulating substrate, and a semiconductor element independently provided on the semiconductor layers. Further, a trench ... | 06/27/2006 |
| 7056802 | Method for fabricating a trench capacitor with an insulation collar which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell The present invention provides a method for fabricating a trench capacitor with an insulation collar (10; 10a, 10b) in a substrate (1), which is electrically connected to the substrate (1) on one side via a buried contact ( | 06/06/2006 |
| 7045417 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device, which comprises forming a first semiconductor film on a surface of a semiconductor substrate, adsorbing a first impurity on a surface of the first semiconductor film, adsorbing a second impurity on the surface of the... | 05/16/2006 |
