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| Number | Title | Issue Date |
| 7439145 | Tunable semiconductor diodes A diode structure fabrication method. In a Pā substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an Nā layer is formed. Then, a P+ region is formed to serve as an a... | 10/21/2008 |
| 7419881 | Phase changeable memory device and method of formation thereof In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern... | 09/02/2008 |
| 7323751 | Thin film resistor integration in a dual damascene structure A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over t... | 01/29/2008 |
| 7307024 | Flash memory and fabrication method thereof A flash memory and a fabrication method thereof, which is capable of improving a whole capacitance of the flash memory by forming a tunneling oxide and a floating gate only in a portion where injection of electrons occurs. A flash memory wherein a tunneling oxide an... | 12/11/2007 |
| 7300836 | Manufacturing method of semiconductor device This invention is directed to a manufacturing method of a semiconductor device having a MOS transistor and a diffusion resistance layer formed on a same semiconductor substrate, where current leakage from the diffusion resistance layer is minimized. The manufacturin... | 11/27/2007 |
| 7259076 | High-density SOI cross-point memory fabricating method A method for fabricating a high-density silicon-on-insulator (SOI) cross-point memory array and an array structure are provided. The method includes the following steps: selectively forming a hard mask on an SOI substrate, defining memory areas, active device areas,... | 08/21/2007 |
| 7253357 | Pulsed voltage surge resistant magnet wire A magnet wire including at least one conductor and at least one insulating layer. The insulating layer includes (a) at least a polymeric resin; (b) at least a fluorinated organic filler; and (c) at least a non-ionic fluorinated surfactant. The magnet wire is endowed... | 08/07/2007 |
| 7250333 | Method of fabricating a linearized output driver and terminator A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includ... | 07/31/2007 |
| 7241663 | Maskless multiple sheet polysilicon resistor The present invention facilitates semiconductor fabrication of semiconductor devices having polysilicon resistors. An oxide layer is formed over a semiconductor device (104). A polysilicon layer is formed on the oxide layer (106). The polysilicon layer... | 07/10/2007 |
| 7235847 | Semiconductor device having a gate with a thin conductive layer A semiconductor device (10) having a gate (16, 18 or 16, 18, 26, 28) with a thin conductive layer (18) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics ( | 06/26/2007 |
| 7208814 | Resistive device and method for its production A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current pa... | 04/24/2007 |
| 7163868 | Method for forming a lightly doped drain in a thin film transistor In accordance with the present invention, a gate electrode structure with inclined planes is used as a mask when performing an ion implantation process. The inclined planes are used to define the lightly doped drain (LDD) region in the active area. Therefore, the wi... | 01/16/2007 |
| 7135367 | Manufacturing method of semiconductor device A silicon oxide film as an insulating film is accumulated so as to cover a whole surface of a silicon substrate including a surface of a resistance element by, for example, a thermal CVD method, just after a resist pattern is removed. This silicon oxide film is proc... | 11/14/2006 |
| 7071070 | Method of fabricating capacitor A method of fabricating a capacitor is described. A dielectric layer is formed over a substrate. An upper electrode having multiple openings therein is formed over the dielectric layer. Then, a doping step is performed to the substrate through the openings to form a... | 07/04/2006 |
| 7064414 | Heater for annealing trapped charge in a semiconductor device A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heatin... | 06/20/2006 |
| 7059859 | Manufacturing method of semiconductor device In a semiconductor device having a MOS transistor and a diffused resistor layer, a leakage current of a diffused resistor layer is suppressed. A film of gate electrode material is formed over the entire surface of an N-type well, a photoresist layer is formed to mas... | 06/13/2006 |
| 7029956 | Memory system capable of operating at high temperatures and method for fabricating the same A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each... | 04/18/2006 |
| 7029830 | Precision and apertures for lithographic systems Aperture members are provided wherein there is thin 1ā10 micrometer thick crystaline membrane that is surrounded by a frame of a bulk type crystalline material. The aperture being an opening through the membrane in a typical shape useful for device fabrication, su... | 04/18/2006 |
| 7030728 | Layout and method to improve mixed-mode resistor performance A resistor layout and method of forming the resistor are described which achieves improved resistor characteristics, such as resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilico... | 04/18/2006 |
| 7005712 | Method for manufacturing a semiconductor device A semiconductor device of the present invention includes a semiconductor layer 10, an insulation gate type heavy insulated transistor 200 and an insulation gate type light insulated transistor 300 having different drain-source breakdown voltages... | 02/28/2006 |
| 7002235 | Semiconductor device A semiconductor device has a semiconductor support substrate, a buried insulation film disposed on the semiconductor support substrate, and a single-crystal silicon active layer disposed on the buried insulation film. The buried insulation film has portions which ha... | 02/21/2006 |
| 6984869 | High performance diode implanted voltage controlled p-type diffusion resistor The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains first and second contact regions extending downward from the surface of the substrate. Third and fourth contacts are ... | 01/10/2006 |
| 6979879 | Trim zener using double poly process In a zener zap diode device and a system for making such a device using a double poly process, p+ and n+regions are formed in a tub by means of p-doped and n-doped polysilicon regions, and a p-n junction is formed between the p+ region and an n-tub or between the n+... | 12/27/2005 |
| 6936520 | Method for fabricating semiconductor device having gate electrode together with resistance element A method for fabricating a semiconductor device comprises the steps of forming a polysilicon film 32 on a silicon substrate 10, implanting a dopant into a region of the polysilicon film 32 for a resistance element to be formed in, patterning the... | 08/30/2005 |
| 6900088 | Semiconductor device and its manufacture method First and second gate electrodes are formed on first and second regions of a semiconductor substrate. Second conductivity type impurities are implanted into the second region to form first impurity diffusion regions. Spacer films are formed on the side surfaces of t... | 05/31/2005 |
| 6835632 | Semiconductor device and process of producing the same The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same... | 12/28/2004 |
| 6784044 | High dopant concentration diffused resistor and method of manufacture therefor The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub loc... | 08/31/2004 |
| 6784066 | Method for manufacturing semiconductor device and semiconductor device manufactured thereby A plurality of gate electrodes is formed on a semiconductor substrate having a DRAM area and a logic area. Next, sidewalls, each of which includes a silicon nitride film covering the sides of gate electrodes and a silicon oxide film covering the silicon nitride film... | 08/31/2004 |
| 6734075 | CMOS device having high-density resistance elements A CMOS device includes a reverse electric conduction type well (2) formed on a monoelectric conduction type semiconductor substrate (1), a first MOS transistor (3) of a reverse electric conduction type channel formed on a surface of the semicond... | 05/11/2004 |
| 6734076 | Method for thin film resistor integration in dual damascene structure A thin film resistor (55) is formed over an etch stop layer 40. Contact pads (65) are formed n the thin film resistor (55) and a dielectric layer (80) is formed over the thin film resistor (55). Metal structures (120 ... | 05/11/2004 |
| 6720228 | Current source bias circuit with hot carrier injection tracking A current mirror bias circuit for an RF amplifier transistor is modified whereby the reference transistor of the current mirror tracks hot carrier degradation in the RF transistor. Gate bias to the current mirror transistor is modified whereby the drain-to-gate volt... | 04/13/2004 |
| 6690082 | High dopant concentration diffused resistor and method of manufacture therefor The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a do... | 02/10/2004 |
| 6667217 | Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step,... | 12/23/2003 |
| 6642604 | Semiconductor device with resistor layer having heat radiation path to semiconductor substrate A resistor layer (5) is formed on an isolation insulating film (4) selectively formed in a major surface (1S) of a semiconductor substrate (1). An interlayer insulation film (7) covering the resistor layer (5) has first and second plugs (9, 19) buried the... | 11/04/2003 |
| 6583019 | Perimeter anchored thick film pad A thick film circuit with a perimeter anchored thick film pad is provided. The thick film circuit includes a base substrate, a thick film bonding pad, and a solder mask layer. The thick film bonding pad is formed on the surface of the base substrate. The ... | 06/24/2003 |
| 6579775 | Semiconductor device having a metal gate with a work function compatible with a semiconductor device The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electro... | 06/17/2003 |
| 6573149 | Semiconductor device having a metal gate with a work function compatible with a semiconductor device The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electro... | 06/03/2003 |
| 6528834 | Container capacitor structure and method of formation thereof Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess betwee... | 03/04/2003 |
| 6500723 | Method for forming a well under isolation and structure thereof A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semicond... | 12/31/2002 |
| 6432766 | Method of fabricating a SRAM device The present invention comprises an improved method of forming the source voltage lines, connection lines, and high load resistors for use in HLR SRAM devices. The source voltage lines, connection lines, and high load resistors are formed from a single pol... | 08/13/2002 |
