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| Number | Title | Issue Date |
| 7488663 | Semiconductor article and method for manufacturing with reduced base resistance A method for manufacturing a semiconductor article and a semiconductor article is provided, wherein a base region of a first semiconductor material is applied, a silicide layer is applied above the base region, after the application of the silicide layer, an opening... | 02/10/2009 |
| 7303949 | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown ... | 12/04/2007 |
| 7241660 | Manufacturing method of semiconductor device A manufacturing method of a semiconductor device having a semiconductor memory including a plurality of nonvolatile memory elements, comprising a step of forming a mask on the semiconductor memory and a step of irradiating through the mask with electron beams, the m... | 07/10/2007 |
| 7184853 | Lithography method and system with correction of overlay offset errors caused by wafer processing A method of controlling lithographic overlay offsets in the manufacture of semiconductor devices from wafers, comprising the steps of forming a lithographic pattern on a wafer layer with a lithographic tool, processing the wafer after the pattern is formed to enable... | 02/27/2007 |
| 7067383 | Method of making bipolar transistors and resulting product A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a ... | 06/27/2006 |
| 7037748 | CMOS image sensor and method for manufacturing the same A CMOS image sensor and a manufacturing method thereof, wherein the gates of several transistors of the CMOS image sensor are formed in an active region defined by an isolation region for a unit pixel of the CMOS image sensor, and a passivation layer composed of ins... | 05/02/2006 |
| 7033903 | Method and apparatus for forming patterned photoresist layer A method for forming a patterned photoresist layer aligned with a predetermined layer is described. A photoresist layer is formed on a substrate and then exposed. The overlay offset between the exposed portions of the photoresist layer and the predetermined layer is... | 04/25/2006 |
| 6913872 | Dual-wavelength exposure for reduction of implant shadowing A method for generating a photoresist structure is disclosed in which a layer of photoresist is deposited over a semiconductor substrate. In a first exposure, the layer of photoresist is exposed to deep ultraviolet light. A second exposure is then performed using a ... | 07/05/2005 |
| 6890826 | Method of making bipolar transistor with integrated base contact and field plate A method of manufacturing a bipolar junction transistor results in an integrated polysilicon base contact and field plate element minimally spaced from a polysilicon emitter contact by using a single mask to define respective openings for these elements. In particul... | 05/10/2005 |
| 6872645 | Methods of positioning and/or orienting nanostructures Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and p... | 03/29/2005 |
| 6835606 | Low temperature polysilicon thin film transistor and method of forming polysilicon layer of same A low temperature polysilicon thin film transistor and a method of forming the polysilicon layer inside the thin film transistor. An amorphous silicon layer is formed over a panel. The panel has a display region and a peripheral circuit region. A metallic layer is f... | 12/28/2004 |
| 6432790 | Method of manufacturing photomask, photomask, and method of manufacturing semiconductor integrated circuit device The reliability of a photomask is improved. The planar shape of a mask substrate 1 of a resist shading mask having a shading pattern composed of a resist film is made circular.... | 08/13/2002 |
| 6337252 | Semiconductor device manufacturing method There is provided a method of manufacturing a semiconductor device which can use commonly a part of a step of forming a PAP transistor with a step of forming an NON transistor. In an area separated by a side separation region (5) of PNP formed by doping N... | 01/08/2002 |
| 6329260 | Analog-to-digital converter and method of fabrication An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are fo... | 12/11/2001 |
| 6251739 | Integrated circuit, components thereof and manufacturing method The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or... | 06/26/2001 |
| 6180442 | Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer... | 01/30/2001 |
| 6077746 | Using p-type halo implant as ROM cell isolation in flat-cell mask ROM process A method for forming a p-type halo implant as ROM cell isolation in a flat-cell mask ROM process is described. A P-well is formed within a semiconductor substrate and an oxide layer is formed overlying a surface of the substrate. A photomask is formed ove... | 06/20/2000 |
| 6043130 | Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base throu... | 03/28/2000 |
| 6001700 | Method and mask structure for self-aligning ion implanting to form various device structures A method for making self-aligned sub-micrometer bipolar transistors and FETs on a substrate for BiFET and BiCMOS circuits was achieved using a novel LOCOS structure as a self-aligned implant mask. This LOCOS structure uses a silicon nitride mask comprised... | 12/14/1999 |
| 5885880 | Bipolar transistor device and method for manufacturing the same A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is ... | 03/23/1999 |
| 5846858 | SOI-BiCMOS method In a manufacturing method for lateral bipolar transistors on an SOI substrate, a ridge-shaped gate electrode (8/9) is applied onto a mesa (3) provided with a basic doping and is covered surface-wide with a TEOS layer (10) that has vertical portions functi... | 12/08/1998 |
| 5837590 | Isolated vertical PNP transistor without required buried layer A vertical PNP transistor and method for making it provide a transistor in a surface layer (12), which may be an epitaxial layer, of P- type conductivity at a surface of a substrate (11) of P+ type conductivity. An isolation region (14) of N- type conduct... | 11/17/1998 |
| 5726922 | Assembly for removably connecting data storage devices An assembly for removably connecting data storage devices is provided for coupling a plurality of such devices within a computer or file server. The assembly comprises a plurality of trays each having a data storage device and a first electrical connector... | 03/10/1998 |
| 5688709 | Method for forming composite trench-fin capacitors for DRAMS A semiconductor memory device capacitor is disclosed which has a trench capacitor portion provided in a semiconductor substrate and a fin capacitor portion provided above the substrate. The trench capacitor portion includes (i) a trench extending from an ... | 11/18/1997 |
| 5593906 | Method of processing a polysilicon film on a single-crystal silicon substrate A method of processing a polysilicon film formed on a single-crystal silicon substrate which can remove the polysilicon film with good selectivity in a fabrication process of semiconductor devices. First, a polysilicon film having an N-portion to be remov... | 01/14/1997 |
| 5589409 | Fabrication of bipolar transistors with improved output current-voltage characteristics A special two-dimensional intrinsic base doping profile is utilized to improve the output current-voltage characteristics of a vertical bipolar transistor whose intrinsic base includes a main intrinsic portion. The special doping profile is achieved with ... | 12/31/1996 |
| 5569613 | Method of making bipolar junction transistor A structural configuration and fabrication process of a bipolar junction transistor (BJT) semiconductor device having improved current gain. The fabrication process provides a P-type heavily-doped region underneath a P-type lightly-doped base region. The ... | 10/29/1996 |
| 5336632 | Method for manufacturing capacitor and bipolar transistor A lower electrode of a capacitor is manufactured simultaneously with an electrode such as a collector electrode and a base electrode of a bipolar transistor, and an upper electrode of the capacitor is manufactured simultaneously with another electrode suc... | 08/09/1994 |
| 5296388 | Fabrication method for semiconductor devices A fabrication method for semiconductor devices connecting a multi-crystal semiconductor thin film and a semiconductor region including a high density of an impurity formed in a single crystal semiconductor substrate. After forming a N-type semiconductor r... | 03/22/1994 |
| 5254485 | Method for manufacturing bipolar semiconductor device There is disclosed a method for manufacturing a bipolar semiconductor device in which emitter region and active base region are formed by implanting impurities of first and second conduction types in a first semiconductor region of the first conduction ty... | 10/19/1993 |
| 5252517 | Method of conductor isolation from a conductive contact plug The method of the present invention introduces a fabrication method for providing capacitor cell polysilicon isolation from a polysilicon contact plug in a semiconductor fabrication process, by providing a contact opening through a first insulating layer,... | 10/12/1993 |
| 5091321 | Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit A vertical NPN transistor is fabricated in a silicon integrated circuit substrate growing an N-type epitaxial layer, forming a preliminary P-type base region in the surface of the epitaxial layer, covering the surface with a protective glass layer, select... | 02/25/1992 |
| 5077227 | Semiconductor device and method for fabricating the same Disclosed is a structure of a semiconductor integrated circuit such as bipolar transistor, along with the fabrication thereof, in which an active device region such an intrinsic base is formed from, at least, the bottom of the groove formed in a semicondu... | 12/31/1991 |
| 5071780 | Reverse self-aligned transistor integrated circuit A method of forming self-aligned transistors which may be either bipolar or field effect is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to ... | 12/10/1991 |
| 5064774 | Self-aligned bipolar transistor process A fully self-aligned bipolar transistor having low emitter and base-resistances is formed in a semiconductor device. In one embodiment, a patterned masking layer is formed on an active device region of a semiconductor substrate. The patterned masking laye... | 11/12/1991 |
| 5019523 | Process for making polysilicon contacts to IC mesas Disclosed is a process for making a bipolar transistor which comprises an n-type Si semiconductor body having a convex portion, an insulation film covering the surface of the semiconductor body other than the convex portion, and a p-type polycrystalline S... | 05/28/1991 |
| 4952521 | Process for fabricating a semiconductor device with selective growth of a metal silicide A metal or metal silicide layer (37) is selectively grown on a nucleating layer (28) with a predetermined pattern on an insulating layer and on a substrate below an opening in an insulating layer, to form a metal or metal silicide electrode in contact wit... | 08/28/1990 |
| 4898837 | Method of fabricating a semiconductor integrated circuit A method of fabricating a semiconductor integrated circuit comprises the steps of: forming buried layers in predetermined regions of a semiconductor substrate; forming an epitaxial layer covering the substrate and the buried layers; forming isolation regi... | 02/06/1990 |
| 4824794 | Method for fabricating a bipolar transistor having self aligned base and emitter A bipolar transistor having self-aligned base and emitter regions is fabricated in a silicon layer which is epitaxially grown on a substrate so as to fill up a cavity formed through a polysilicon layer deposited on the substrate. The polysilicon layer is ... | 04/25/1989 |
| 4804634 | Integrated circuit lateral transistor structure In a monolithic silicon integrated circuit fast diffusing impurities are incorporated into the collectors of the bipolar lateral transistors. The impurity level is controlled, using ion implantation, so that after device processing the lateral transistor ... | 02/14/1989 |
