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| Number | Title | Issue Date |
| 8003476 | Semiconductor device having a plurality of kinds of wells and manufacturing method thereof A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than t... | 08/23/2011 |
| 7615458 | Activation of CMOS source/drain extensions by ultra-high temperature anneals A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount ... | 11/10/2009 |
| 7384853 | Method of performing salicide processes on MOS transistors A method of performing salicide processes on a MOS transistor, wherein the MOS transistor comprises a gate structure and a source/drain region, the method comprising: performing a selective growth process to form a silicon layer on the top of the gate and the source... | 06/10/2008 |
| 7338876 | Method for manufacturing a semiconductor device A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor subs... | 03/04/2008 |
| 7288829 | Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the... | 10/30/2007 |
| 7271070 | Method for producing transistors The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is de... | 09/18/2007 |
| 7195986 | Microfluidic device with controlled substrate conductivity A method to achieve controlled conductivity in microfluidic devices, and a device formed thereby. The method comprises forming a microchannel or a well in an insulating material, and ion implanting at least one region of the insulating material at or adjacent the mi... | 03/27/2007 |
| 6995068 | Double-implant high performance varactor and method for manufacturing same A varactor designed to enable voltage controlled oscillator (VCO) integration in wireless systems is the base-emitter junction of a specially optimized NPN device formed with a double base implant. A first, shallow implant optimizes capacitance, leakage current, and... | 02/07/2006 |
| 6893934 | Bipolar transistor device having phosphorous A Si1-xGex layer 111b functioning as the base composed of an i—Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111 | 05/17/2005 |
| 6716712 | Process for producing two differently doped adjacent regions in an integrated semiconductor During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for producing two adjacent regions of a predetermined area in an integrated semiconductor, whereby a first regi... | 04/06/2004 |
| 6337252 | Semiconductor device manufacturing method There is provided a method of manufacturing a semiconductor device which can use commonly a part of a step of forming a PAP transistor with a step of forming an NON transistor. In an area separated by a side separation region (5) of PNP formed by doping N... | 01/08/2002 |
| 6329257 | Method for laterally peaked source doping profiles for better erase control in flash memory devices A system and method for controlling a characteristic of at least one memory cell on a semiconductor is disclosed. The at least one memory cell includes a gate stack, a source, and a drain. The semiconductor includes a surface. In one aspect, the method an... | 12/11/2001 |
| 6309940 | Latch-up resistant CMOS structure Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the... | 10/30/2001 |
| 6225180 | Semiconductor device and method of manufacturing the same A photoresist pattern is formed on a field oxide film and an element forming region across the field oxide film and the element forming region such that a portion of a surface of the field oxide film and a portion of a surface of a silicon epitaxial layer... | 05/01/2001 |
| 6215151 | Methods of forming integrated circuitry and integrated circuitry Integrated circuitry and methods of forming integrated circuitry are described. In one implementation, a common masking step is utilized to provide source/drain diffusion regions and halo ion implantation or dopant regions relative to the source/drain reg... | 04/10/2001 |
| 6146953 | Fabrication method for mosfet device A fabrication method for a MOSFET device including the steps of forming a first insulating film on a semiconductor substrate wherein an active region and an isolated region are defined, forming a channel ion region by implanting impurity ions into the act... | 11/14/2000 |
| 6043130 | Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base throu... | 03/28/2000 |
| 5976921 | Method for manufacturing electrostatic discharge protection (ESD) and BiCMOS A semiconductor device having an electrostatic discharge protection device and at least one accompanying device selected from the group comprising of a N or P channel MOS transistor, CMOS, bipolar transistor and BiCMOS, in which the electrostatic discharg... | 11/02/1999 |
| 5885880 | Bipolar transistor device and method for manufacturing the same A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is ... | 03/23/1999 |
| 5850242 | Recording head and recording apparatus and method of manufacturing same The occupied area of a heater drive circuit of a recording head is reduced, and the number of manufacturing steps is decreased. As a circuitry of the heater drive unit, the final stage of the drive unit is constituted of a pnp or npn bipolar transistor, t... | 12/15/1998 |
| 5780329 | Process for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional mask A bipolar transistor with a relatively deep emitter region is formed in a BICMOS device using the source/drain mask used to form the source and drain regions of MOSFETs of the device and the base region mask which would otherwise be required in any event ... | 07/14/1998 |
| 5756387 | Method for forming zener diode with high time stability and low noise Zener diode with high stability in time and low noise for integrated circuits and provided in an epitaxial pocket insulated from the rest of a type N epitaxial layer grown on a substrate of type P semiconductor material. In said pocket are included a type... | 05/26/1998 |
| 5700730 | Semiconductor processing method of providing dopant impurity into a semiconductor substrate A semiconductor processing method of providing dopant impurity into a semiconductor substrate includes: a) providing a semiconductor substrate, the substrate comprising a first bulk region having a blanket doping of a first conductivity type dopant, the s... | 12/23/1997 |
| 5593905 | Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as... | 01/14/1997 |
| 5569612 | Process for manufacturing a bipolar power transistor having a high breakdown voltage There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate of the N type, over which a lightly doped N type layer, constituting a collector region of the transistor, is superimposed. The ... | 10/29/1996 |
| 5496746 | Method for fabricating a bipolar junction transistor exhibiting improved beta and punch-through characteristics A bipolar transistor having an emitter, a base, and a collector includes an intrinsic base region having narrow side areas and a wider central area. The side areas are located adjacent to the extrinsic base region, while the central area is disposed under... | 03/05/1996 |
| 5453387 | Fabrication method of semiconductor device with neighboring n- and p-type regions A fabrication method of a semiconductor device that can form n- and p-type buried regions separately in a semiconductor substrate of a first conductivity type through a single lithography process. A first impurity of a second conductivity type is doped in... | 09/26/1995 |
| 5279976 | Method for fabricating a semiconductor device having a shallow doped region A method is provided for the formation of ultra-shallow boron doped regions in a semiconductor device. In one embodiment of the invention an N-type semiconductor substrate (15) is provided having a first P-type region formed therein. A dielectric layer (1... | 01/18/1994 |
| 5137840 | Vertical bipolar transistor with recessed epitaxially grown intrinsic base region A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the... | 08/11/1992 |
| 5128272 | Self-aligned planar monolithic integrated circuit vertical transistor process A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isol... | 07/07/1992 |
| 5098638 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device forms an intrinsic base layer by doping an impurity in the emitter polysilicon electrode into the intrinsic base region of the surface of a semiconductor substrate by heat treatment through the emitter lead... | 03/24/1992 |
| 5064774 | Self-aligned bipolar transistor process A fully self-aligned bipolar transistor having low emitter and base-resistances is formed in a semiconductor device. In one embodiment, a patterned masking layer is formed on an active device region of a semiconductor substrate. The patterned masking laye... | 11/12/1991 |
| 5039624 | Method of manufacturing a bipolar transistor A bipolar transistor having an intrinsic base portion for forming emitter-base PN junction with an emitter region and an extrinsic base portion for connecting a base electrode is disclosed. A concavity is formed between the intrinsic and extrinsic base po... | 08/13/1991 |
| 5023192 | Method of manufacturing a bipolar transistor A first device region (20) of one conductivity type is provided adjacent one major surface (11) of a semiconductor body (10). A layer (30) doped with impurities of the opposite conductivity type is provided on the one major surface (11) for forming an ext... | 06/11/1991 |
| 5019523 | Process for making polysilicon contacts to IC mesas Disclosed is a process for making a bipolar transistor which comprises an n-type Si semiconductor body having a convex portion, an insulation film covering the surface of the semiconductor body other than the convex portion, and a p-type polycrystalline S... | 05/28/1991 |
| 5010026 | Process for making bipolar transistor A bipolar transistor has a base region consisting of a graft base region, linking base region and an intrinsic base region, and a diffusion suppressing region of an opposite conductivity type to that of the base region is formed at least at the lower port... | 04/23/1991 |
| 4946798 | Semiconductor integrated circuit fabrication method In a semiconductor integrated circuit fabrication method, isolated regions are in a silicon substrate, which is then covered with polysilicon, a passive base region is then formed, the polysilicon is selectively oxidized, the unoxidized polysilicon is the... | 08/07/1990 |
| 4902640 | High speed double polycide bipolar/CMOS integrated circuit process A mixed bipolar-CMOS self-aligned process and integrated circuit provide a high performance NPN bipolar transistor in parallel to fabrication of a PMOSFET and an NMOSFET. Gate and base contacts are formed in a first polysilicon layer. The base contacts ar... | 02/20/1990 |
| 4849364 | Semiconductor devices A method of manufacturing a bipolar transistor (1) with semi-self-aligned p+ base contacts (27,27a). A p-type base region (28) is formed in a surface region of an n-type region 5 comprising a collector. An element (29) of, for example, n+... | 07/18/1989 |
| 4830972 | Method of manufacturing bipolar transistor A method of manufacturing an ultra-miniaturized bipolar transistor is disclosed, wherein an insulating film and a first polysilicon film doped with an impurity of a second conductivity type are formed, in this order, as a collector on a semiconductor laye... | 05/16/1989 |
