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| Number | Title | Issue Date |
| 7384853 | Method of performing salicide processes on MOS transistors A method of performing salicide processes on a MOS transistor, wherein the MOS transistor comprises a gate structure and a source/drain region, the method comprising: performing a selective growth process to form a silicon layer on the top of the gate and the source... | 06/10/2008 |
| 7378342 | Methods for forming vias varying lateral dimensions Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are formed in a substrate such that the first opening, the second opening... | 05/27/2008 |
| 7150842 | Method of extruding a mixture A method of extruding a mixture made of a granulate, chips, or powder, etc. of a first thermoplastic and a second thermoplastic is described, the melting range of the first thermoplastic differing from the melting range of the second thermoplastic, using an extruder... | 12/19/2006 |
| 7112501 | Method of fabrication a silicon-on-insulator device with a channel stop A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral par... | 09/26/2006 |
| 6847061 | Elimination of implant damage during manufacture of HBT During the conventional manufacture of HBTs, implant damage occurs which leads to enhanced internal base diffusion. This problem has been overcome by making the base and base contact area from a single, uniformly doped layer of silicon-germanium. Instead of an ion i... | 01/25/2005 |
| 6808999 | Method of making a bipolar transistor having a reduced base transit time A bipolar transistor has a high performance and high reliability, which are obtained by enhancing a withstanding voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, an opening dispose... | 10/26/2004 |
| 6764918 | Structure and method of making a high performance semiconductor device having a narrow doping profile A structure and method of making an NPN heterojunction bipolar transistor (100) includes a semiconductor substrate (11) with a first region (82) containing a dopant (86) for forming a base region of the transistor. A second region (84 | 07/20/2004 |
| RE38510 | Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip The device uses the horizontal insulating region and the buried layer as the power transistor base and emitter respectively. An epitaxial growth is interposed between the two diffusions needed to form the aforesaid regions and those needed to create the base and the... | 05/04/2004 |
| 6610578 | Methods of manufacturing bipolar transistors for use at radio frequencies A bipolar transistor of type NPN has an active region at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas. The active region is partly covered by an electrica... | 08/26/2003 |
| 6506659 | High performance bipolar transistor In one disclosed embodiment, a collector is deposited and a base is grown on the collector, for example, by epitaxially depositing either silicon or silicon-germanium. An emitter is fabricated on the base followed by implant doping an extrinsic base regio... | 01/14/2003 |
| 6459140 | Indium-enhanced bipolar transistor A method to improve the characteristics of bipolar silicon high-frequency transistor by adding indium into the base of the transistor is described. Instead of replacing boron in the base with indium to improve the beta-Early voltage product, at the price ... | 10/01/2002 |
| 6368929 | Method of manufacturing a semiconductor component and semiconductor component thereof A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (6... | 04/09/2002 |
| 6329260 | Analog-to-digital converter and method of fabrication An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are fo... | 12/11/2001 |
| 6180442 | Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer... | 01/30/2001 |
| 6180470 | FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements Lifetime of a short-channel NMOS device is increased by modifying distributions of electrically active LDD dopant at boundaries of the device's LDD regions. The LDD dopant distributions are modified by implanting counter-dopants at the boundaries of the L... | 01/30/2001 |
| 6156594 | Fabrication of bipolar/CMOS integrated circuits and of a capacitor The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, ope... | 12/05/2000 |
| 6043130 | Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base throu... | 03/28/2000 |
| 5950080 | Semiconductor device and method of manufacturing the same In a semiconductor device manufacturing method, a buried collector region (5) of a bipolar transistor is formed, and then born is ion-implanted into at least the lower portion of a graft base region (15) to form a region (10) having a low donor concentrat... | 09/07/1999 |
| 5885880 | Bipolar transistor device and method for manufacturing the same A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is ... | 03/23/1999 |
| 5856228 | Manufacturing method for making bipolar device having double polysilicon structure A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor dev... | 01/05/1999 |
| 5837590 | Isolated vertical PNP transistor without required buried layer A vertical PNP transistor and method for making it provide a transistor in a surface layer (12), which may be an epitaxial layer, of P- type conductivity at a surface of a substrate (11) of P+ type conductivity. An isolation region (14) of N- type conduct... | 11/17/1998 |
| 5726069 | Use of oblique implantation in forming emitter of bipolar transistor A bipolar transistor is fabricated by a process in which first and second dopants of the same conductivity type are introduced into a semiconductor body through at least partially overlapping sections, preferably the same section, of the body's upper surf... | 03/10/1998 |
| 5569613 | Method of making bipolar junction transistor A structural configuration and fabrication process of a bipolar junction transistor (BJT) semiconductor device having improved current gain. The fabrication process provides a P-type heavily-doped region underneath a P-type lightly-doped base region. The ... | 10/29/1996 |
| 5492844 | Method of manufacturing increased conductivity base contact/feeders with self-aligned structures A very deep P+ diffusion step is performed prior to the definition of a self-aligning emitter/P+ region. Furthermore, the initial P+ region is formed with dimensions sufficiently narrow to allow the subsequent emitter/P | 02/20/1996 |
| 5482873 | Method for fabricating a bipolar power transistor A method for fabricating a bipolar power transistor is disclosed, wherein the bipolar power transistor is made on a first type of heavily doped substrate. The method comprises the following steps of: sequentially forming a first type of doped layer, a fir... | 01/09/1996 |
| 5453387 | Fabrication method of semiconductor device with neighboring n- and p-type regions A fabrication method of a semiconductor device that can form n- and p-type buried regions separately in a semiconductor substrate of a first conductivity type through a single lithography process. A first impurity of a second conductivity type is doped in... | 09/26/1995 |
| 5336926 | Bipolar junction exhibiting suppressed kirk effect A bipolar junction transistor (BJT) which exhibits a suppressed Kirk Effect comprises a lightly-doped n-type collector region formed above a more heavily-doped n+ layer. Directly above the collector is a p-type base which has an extrinsic region disposed ... | 08/09/1994 |
| 5286660 | Method for doping a semiconductor wafer having a diffusivity enhancement region A diffusivity and a solubility of dopant atoms are increased within a semiconductor wafer (30). A portion (36) of the semiconductor wafer (30) is disrupted by a technique of ion implantation thereby forming a defect layer (36). A predeposition layer (37) ... | 02/15/1994 |
| 5273934 | Method for producing a doped region in a substrate A doped region (14) is produced in a substrate (11) of silicon by diffusion of dopant from a doped glass layer (13) that is arranged on an intermediate layer (12) situated on the substrate (11) . The dopant concentration in the doped region (14) is thereb... | 12/28/1993 |
| 5183768 | Method of fabricating semiconductor device by forming doped regions that limit width of the base A first semiconductor region is of a first conduction type and forms a transistor collector. A second semiconductor region is of a second conduction type and forms a transistor base. The second semiconductor region extends in the first semiconductor regio... | 02/02/1993 |
| 5098638 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device forms an intrinsic base layer by doping an impurity in the emitter polysilicon electrode into the intrinsic base region of the surface of a semiconductor substrate by heat treatment through the emitter lead... | 03/24/1992 |
| 5096843 | Method of manufacturing a bipolar CMOS device A well with a low impurity concentration is provided as a collector region on a semiconductor substrate. A trench is formed in a portion of the well from the surface toward the inside thereof. An insulating film, serving as a barrier against impurities, i... | 03/17/1992 |
| 5091321 | Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit A vertical NPN transistor is fabricated in a silicon integrated circuit substrate growing an N-type epitaxial layer, forming a preliminary P-type base region in the surface of the epitaxial layer, covering the surface with a protective glass layer, select... | 02/25/1992 |
| 5077227 | Semiconductor device and method for fabricating the same Disclosed is a structure of a semiconductor integrated circuit such as bipolar transistor, along with the fabrication thereof, in which an active device region such an intrinsic base is formed from, at least, the bottom of the groove formed in a semicondu... | 12/31/1991 |
| 5064773 | Method of forming bipolar transistor having closely spaced device regions A method of forming a bipolar transistor. A base region is implanted into an epitaxial layer. An emitter and collector contact regions are formed of doped polysilicon on the epitaxial layer, the emitter being formed over the base region. The implant is be... | 11/12/1991 |
| 5061646 | Method for forming a self-aligned bipolar transistor A structure and process for fabricating a fully self-aligned high-performance bipolar semiconductor device is disclosed. In accordance with one embodiment of the invention, a substrate is provided having a first surface. A heavily doped buried layer is fo... | 10/29/1991 |
| 5055419 | Method of manufacturing a bipolar transistor A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p+ base contact... | 10/08/1991 |
| 5047357 | Method for forming emitters in a BiCMOS process A bipolar transistor and method of making the same is disclosed. The transistor has an emitter region which is diffused from polysilicon into the intrinsic base region, where the polysilicon is doped with two dopant species of different diffusivity. The i... | 09/10/1991 |
| 5045484 | Fabrication method of a BIMOS semiconductor device A method for fabricating a BIMOS device includes steps of forming a first insulator layer on the semiconductor layer in correspondence to a first region, providing a gate electrode of a metal-insulator-semiconductor transistor on the first insulator layer... | 09/03/1991 |
| 5026654 | Method of manufacturing a semiconductor device utilizing a single polycrystalline layer for all electrodes Disclosed is here a semicondutor integrated circuit device and a method of manufacturing the same in which bipolar transistors and MISFETs are formed on a semiconductor substrate. Emitter and base electrodes of the bipolar transistors and gate, source, an... | 06/25/1991 |
