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Vladimir Zworykin, television pioneer ; Talking about an invention in which he played a critical role.
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| Number | Title | Issue Date |
| 7384853 | Method of performing salicide processes on MOS transistors A method of performing salicide processes on a MOS transistor, wherein the MOS transistor comprises a gate structure and a source/drain region, the method comprising: performing a selective growth process to form a silicon layer on the top of the gate and the source... | 06/10/2008 |
| 7354841 | Method for fabricating photodiode of CMOS image sensor A method for fabricating a photodiode of a CMOS image sensor is disclosed, to improve a charge accumulation capacity in the photodiode, which includes the steps of defining a semiconductor substrate as an active area and a field area by forming an STI layer; firstly... | 04/08/2008 |
| 7300851 | Method of fabricating a silicon-on-insulator device with a channel stop A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral par... | 11/27/2007 |
| 7288829 | Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the... | 10/30/2007 |
| 7268052 | Method for reducing soft error rates of memory cells In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical ju... | 09/11/2007 |
| 7208793 | Scalable integrated logic and non-volatile memory A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal n... | 04/24/2007 |
| 7207025 | Sea-of-cells array of transistors The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space. ... | 04/17/2007 |
| 7169654 | Method of forming a semiconductor device A method of integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate includes forming openings within an active semiconductor layer in first and second regions of a semiconductor substrate. The first region corresponds to a n... | 01/30/2007 |
| 7169674 | Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and ... | 01/30/2007 |
| 7112501 | Method of fabrication a silicon-on-insulator device with a channel stop A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral par... | 09/26/2006 |
| 7087961 | Semiconductor device with reduced on-state resistance To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed on an N-ty... | 08/08/2006 |
| 7001856 | Method of calculating a pressure compensation recipe for a semiconductor wafer implanter A process uses pressure changes and a pressure compensation factor to estimate the rate at which neutral atoms are implanted. While implanting a first wafer using a first pressure compensation factor, the rate at which ions are implanted is determined. The first waf... | 02/21/2006 |
| 6967361 | Sea-of-cells array of transistors The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space. ... | 11/22/2005 |
| 6927118 | Method of fabricating a bipolar transistor utilizing a dry etching and a wet etching to define a base junction opening The present invention discloses a process of fabricating a semiconductor device comprising the steps of: forming a collector layer of a first conductivity type at a portion of a surface of a semiconductor substrate; forming a collector opening portion in a first ins... | 08/09/2005 |
| 6919260 | Method of manufacturing a substrate having shallow trench isolation A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed at predetermined locations of the semiconductor substrate and oxide ... | 07/19/2005 |
| 6908810 | Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region... | 06/21/2005 |
| 6887765 | Method for manufacturing a bipolar junction transistor According to one embodiment of the invention, a method used in manufacturing an intermediate structure in a bipolar junction transistor includes implanting a base dopant in a semiconductor substrate to form a base, forming a dielectric layer outwardly from the semic... | 05/03/2005 |
| 6777302 | Nitride pedestal for raised extrinsic base HBT process A method of fabricating a high-performance, raised extrinsic base HBT having a narrow emitter width is provided. In accordance with the method, a patterned nitride pedestal region and inner spacers are employed to reduce the width of an emitter opening. The reduced ... | 08/17/2004 |
| 6727165 | Fabrication of metal contacts for deep-submicron technologies Provided is a process for forming a semiconductor device having salicided contacts. A concentration of metal is formed at the substrate surface by exposing the substrate to a metal plasma. The concentration of metal is then annealed to produce a salicided contact. I... | 04/27/2004 |
| 6716727 | Methods and apparatus for plasma doping and ion implantation in an integrated processing system Methods and apparatus are provided for plasma doping and ion implantation in an integrated processing system. The apparatus includes a process chamber, a beamline ion implant module for generating an ion beam and directing the ion beam into the process chamber, a pl... | 04/06/2004 |
| 6716712 | Process for producing two differently doped adjacent regions in an integrated semiconductor During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for producing two adjacent regions of a predetermined area in an integrated semiconductor, whereby a first regi... | 04/06/2004 |
| 6459140 | Indium-enhanced bipolar transistor A method to improve the characteristics of bipolar silicon high-frequency transistor by adding indium into the base of the transistor is described. Instead of replacing boron in the base with indium to improve the beta-Early voltage product, at the price ... | 10/01/2002 |
| 6458667 | High power PMOS device An improved MOS transistor and method for making it are described. The MOS transistor's source and drain have a first conductivity type and are separated from each other by a first region having a second conductivity type opposite to the first conductivit... | 10/01/2002 |
| 6436779 | Semiconductor device having a plurality of resistive paths A semiconductor device has first and second opposed major surfaces (10a and 10b). A semiconductor first region (11) is provided between second (12 or 120) and third (14) regions such that the second region (12 or 120) forms a rectifying junction (13 or 13... | 08/20/2002 |
| 6352887 | Merged bipolar and CMOS circuit and method A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region 211 of a bipolar transistor and a p-well 212 of an n-channel MOS transistor; and forming in a single implantation st... | 03/05/2002 |
| 6265275 | Method of selectively doping the intrinsic collector of a vertical bipolar transistor with epitaxial base The collector of a vertical bipolar transistor is selectively doped by a first implantation of dopants before the epitaxy of the base, and is selectivly doped by a second implantation of dopants through the epitaxial base. Two implanted zones with differe... | 07/24/2001 |
| 6232182 | Non-volatile semiconductor memory device including memory transistor with a composite gate structure and method of manufacturing the same A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region ... | 05/15/2001 |
| 6150200 | Semiconductor device and method of making A semiconductor device (10) is formed in a semiconductor substrate (11) and an epitaxial layer (14). The semiconductor device includes a p-type body region (16), a source region (17), a channel region (19), and a drain region (34) formed in the epitaxial ... | 11/21/2000 |
| 5966599 | Method for fabricating a low trigger voltage silicon controlled rectifier and thick field device A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide laye... | 10/12/1999 |
| 5880002 | Method for making isolated vertical PNP transistor in a digital BiCMOS process A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is... | 03/09/1999 |
| 5866446 | Method of manufacturing bimos device To enable a high speed operation and to increase the current gain, the disclosed a method of manufacturing a semiconductor device, comprising the steps of: forming a first semiconductor layer with a first-conductivity type in a semiconductor substrate; fo... | 02/02/1999 |
| 5846858 | SOI-BiCMOS method In a manufacturing method for lateral bipolar transistors on an SOI substrate, a ridge-shaped gate electrode (8/9) is applied onto a mesa (3) provided with a basic doping and is covered surface-wide with a TEOS layer (10) that has vertical portions functi... | 12/08/1998 |
| 5726922 | Assembly for removably connecting data storage devices An assembly for removably connecting data storage devices is provided for coupling a plurality of such devices within a computer or file server. The assembly comprises a plurality of trays each having a data storage device and a first electrical connector... | 03/10/1998 |
| 5681763 | Method for making bipolar transistors having indium doped base Indium doping is used to make bases of bipolar transistors with superior operational characteristics.... | 10/28/1997 |
| 5571731 | Procedure for the manufacture of bipolar transistors without epitaxy and with fully implanted base and collector regions which are self-positioning relative to each other A method of fabricating a semiconductor device. A series of layers is deposited on a semiconductor substrate of a first conductivity type to form a shielding arrangement, including an upper part and a lower part, to provide a shield against accelerated io... | 11/05/1996 |
| 5569613 | Method of making bipolar junction transistor A structural configuration and fabrication process of a bipolar junction transistor (BJT) semiconductor device having improved current gain. The fabrication process provides a P-type heavily-doped region underneath a P-type lightly-doped base region. The ... | 10/29/1996 |
| 5554543 | Process for fabricating bipolar junction transistor having reduced parasitic capacitance A process for fabricating a BJT device on a semiconductor substrate is disclosed. The substrate serves as the collector. The process comprises the steps of, first, forming a shielding layer over the designated location over the surface of the substrate fo... | 09/10/1996 |
| 5496746 | Method for fabricating a bipolar junction transistor exhibiting improved beta and punch-through characteristics A bipolar transistor having an emitter, a base, and a collector includes an intrinsic base region having narrow side areas and a wider central area. The side areas are located adjacent to the extrinsic base region, while the central area is disposed under... | 03/05/1996 |
| 5492844 | Method of manufacturing increased conductivity base contact/feeders with self-aligned structures A very deep P+ diffusion step is performed prior to the definition of a self-aligning emitter/P+ region. Furthermore, the initial P+ region is formed with dimensions sufficiently narrow to allow the subsequent emitter/P | 02/20/1996 |
| 5482873 | Method for fabricating a bipolar power transistor A method for fabricating a bipolar power transistor is disclosed, wherein the bipolar power transistor is made on a first type of heavily doped substrate. The method comprises the following steps of: sequentially forming a first type of doped layer, a fir... | 01/09/1996 |
