Class 438/356 - Isolation by PN junction only

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a bipolar transistor in a semiconductive
No. of patents: 33
Last issue date: 01/31/2012

Number	Title	Issue Date
8105911	Bipolar junction transistor guard ring structures and method of fabricating thereof Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, t...	01/31/2012
7250323	Methods of making energy conversion devices with a substantially contiguous depletion regions A method of making an energy conversion device includes forming a plurality of pores within a substrate and forming a junction region within each of the plurality of pores. Each of the junction regions has a depletion region and each of the plurality of pores define...	07/31/2007
7179691	Method for four direction low capacitance ESD protection The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Vss protection device. In add...	02/20/2007
7151035	Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a...	12/19/2006
7135364	Method of fabricating semiconductor integrated circuit The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform bas...	11/14/2006
7037798	Bipolar transistor structure with self-aligned raised extrinsic base and methods The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This add...	05/02/2006
6927115	Method of fabricating semiconductor integrated circuit The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform bas...	08/09/2005
6893934	Bipolar transistor device having phosphorous A Si1-xGex layer 111b functioning as the base composed of an i—Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111	05/17/2005
6858510	Low-voltage punch-through bi-directional transient-voltage suppression devices having surface breakdown protection and methods of making the same A method of making a bi-directional transient voltage suppression device is provided, which comprises: (a) providing a p-type semiconductor substrate; (b) epitaxially depositing a lower semiconductor layer of p-type conductivity; (c) epitaxially depositing a middle ...	02/22/2005
6548347	Method of forming minimally spaced word lines A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the t...	04/15/2003
6492710	Substrate isolated transistor A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposit...	12/10/2002
6441446	Device with integrated bipolar and MOSFET transistors in an emitter switching configuration The device is constituted by an N+ substrate, by an N- layer on the substrate, by a metal contact for a collector, by a buried P- base region, by a P+ base contact and insulation region within which an insulated N region is defined, by a metal contact on ...	08/27/2002
6423604	Determination of thermal resistance for field effect transistor formed in SOI technology The thermal resistance Rth parameter is determined for a field effect transistor formed with a semiconductor film on a buried insulating material in SOI (semiconductor on insulator) technology. A p-n junction is formed with one of a drain regio...	07/23/2002
6420771	Trench isolated bipolar transistor structure integrated with CMOS technology A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either ...	07/16/2002
6225181	Trench isolated bipolar transistor structure integrated with CMOS technology A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either ...	05/01/2001
6211028	Twin current bipolar device with hi-lo base profile A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two su...	04/03/2001
6187642	Method and apparatus for making mosfet's with elevated source/drain extensions The inventive method provides improved semiconductor devices, such as MOSFET's with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate. The inventive method provides thin first dielectric spacers...	02/13/2001
6093620	Method of fabricating integrated circuits with oxidized isolation A thin silicon epitaxial layer, formed on a silicon substrate, is subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction....	07/25/2000
5942783	Semiconductor device having improved latch-up protection A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semicondu...	08/24/1999
5895249	Integrated edge structure for high voltage semiconductor devices and related manufacturing process An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a firs...	04/20/1999
5789288	Process for the fabrication of semiconductor devices having various buried regions A process for doping a P-type substrate (50) by forming a layer (52) of silicon nitride, implanting N-type impurities through this layer (FIG. 7), forming a resist mask (54) which leaves at least one area of the substrate (FIG. 8) containing a part of the...	08/04/1998
5679586	Composite mask process for semiconductor fabrication This is a method of making a semiconductor device comprising covering a first semiconductor compound having a plurality of windows on a major surface of a semiconductor body, covering a second semiconductor compound on selected windows of the first compou...	10/21/1997
5624852	Manufacturing process for obtaining integrated structure bipolar transistors with controlled storage time Integrated structure bipolar transistors with controlled storage time are manufactured by forming at least one bipolar transistor occupying a first area on a first surface of the silicon material, covering the first surface of the silicon material with an...	04/29/1997
5605850	Method for making a low-noise bipolar transistor A low-noise PNP transistor comprising a cutoff region laterally surrounding the emitter region in the surface portion of the transistor. The cutoff region has such a conductivity is to practically turn off the surface portion of the transistor, so that th...	02/25/1997
5556796	Self-alignment technique for forming junction isolation and wells A method in accordance with one embodiment of the present invention may be used to self-align isolation regions, sinkers, and wells. In this improved method, P+ isolation regions, N+ sinkers, and P-wells are defined using the same masking step used to def...	09/17/1996
5539301	Monolithically integrated power output stage A monolithically integrated power output stage detects the load current through an output-stage transistor. Switch logic coupled to an output transistor is for switching the output transistor when a predetermined load-current threshold is reached. In this...	07/23/1996
4490182	Semiconductor processing technique for oxygen doping of silicon A process for isolating a semiconductor device formed in a p-type silicon substrate includes implanting a layer of oxygen ions below the device. The substrate is then heated to 430°-470° C. to activate the silicon/oxygen complexes thus formed and compen...	12/25/1984
4456488	Method of fabricating an integrated planar transistor A method is disclosed for fabricating a monolithic integrated planar transistor whose emitter region (1) is diffused into the base region (3) on one surface side of a semiconductor wafer (2), which base region is diffused into the collector region (4). To...	06/26/1984
4418469	Method of simultaneously forming buried resistors and bipolar transistors by ion implantation A method of making at a relatively low temperature, a resistor region of a high sheet resistance, solely or together with other circuit devices such as bipolar transistors in an IC chip, with the step of forming a buried resistor layer inside a semiconduc...	12/06/1983
4239558	Method of manufacturing semiconductor devices utilizing epitaxial deposition and triple diffusion A method of manufacturing a semiconductor device having at least one power transistor and a plurality of small signal transistors formed on the same semiconductor substrate is disclosed. First, a base region of the power transistor and an isolating region...	12/16/1980
4113512	Technique for preventing forward biased epi-isolation degradation Certain types of silicon integrated circuits are embodied as having diffused isolation regions surrounding epitaxial regions. Although normally operated in a reverse bias mode, such regions may become forward biased when sourcing current for certain circu...	09/12/1978
4089103	Monolithic integrated circuit device construction methods Methods for monolithic integrated circuit construction are presented wherein component device-isolating region self-alignment is provided and also, where an element of the device is provided through independent dopant provision steps to allow design flexi...	05/16/1978
3981072	Bipolar transistor construction method A thick layer of silicon dioxide is grown on a semiconductive substrate and then etched to form an elongated opening that defines the outer boundaries of a diffused transistor. The thick silicon dioxide layer serves as a permanent fixed, diffusion mask. T...	09/21/1976

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Class 438/356 - Isolation by PN junction only