Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
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| Number | Title | Issue Date |
| 7390696 | Wafer, semiconductor device, and fabrication methods therefor In order to fabricate a semiconductor device that can perform at its full capacity, in which (i) a single-crystal silicon integrated circuit is formed on an insulating substrate without an adhesive agent, and (ii) an active region of the single-crystal integrated ci... | 06/24/2008 |
| 7358164 | Crystal imprinting methods for fabricating substrates with thin active silicon layers Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the aper... | 04/15/2008 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre... | 04/08/2008 |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7327012 | Bipolar Transistor Devices A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a ... | 02/05/2008 |
| 7282415 | Method for making a semiconductor device with strain enhancement A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the co... | 10/16/2007 |
| 7279769 | Semiconductor device and manufacturing method thereof To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an ele... | 10/09/2007 |
| 7217629 | Epitaxial imprinting The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on ... | 05/15/2007 |
| 7172914 | Method of making uniform oxide layer A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial lay... | 02/06/2007 |
| 7135364 | Method of fabricating semiconductor integrated circuit The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform bas... | 11/14/2006 |
| 7109534 | Transistor and electronic device The invention provides a transistor capable of achieving a higher speed although its construction is easy to manufacture without requiring wiring to intersect three-dimensionally even if unit elements of transistors are connected in parallel, and to provide an elect... | 09/19/2006 |
| 7067383 | Method of making bipolar transistors and resulting product A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a ... | 06/27/2006 |
| 7060585 | Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization A method utilizing in-place bonding and amorphization/templated recrystallization (ATR) is provided for making bulk and semiconductor-on-insulator substrates having coplanar semiconductor layers of different crystallographic orientations. First and second semiconduc... | 06/13/2006 |
| 7056779 | Semiconductor power device A p type base layer is formed in one surface region of an n type base layer. An n type emitter layer is formed in a surface region of the p type base layer. An emitter electrode is formed on the n type emitter layer and the p type base layer. A trench is formed in t... | 06/06/2006 |
| 7022560 | Method to manufacture high voltage MOS transistor by ion implantation A method for fabrication of a high-voltage, high-frequency MOS-transistor combines a deep n-well and a p-well process and the formation of an extended drain region (45), and a channel region (31), the channel having a short length and becoming well ali... | 04/04/2006 |
| 7023029 | Complementary vertical SCRs for SOI and triple well processes In an ESD protection device using a SCR-like structure, a vertical device is provided that is highly robust and easily allows the triggering voltage to be adjusted during manufacture. Furthermore it is implementable in complementary form based on PNP and NPN BJT str... | 04/04/2006 |
| 7001825 | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments,... | 02/21/2006 |
| 6964907 | Method of etching a lateral trench under an extrinsic base and improved bipolar transistor In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer. ... | 11/15/2005 |
| 6955957 | Method of forming a floating gate in a flash memory device Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide fil... | 10/18/2005 |
| 6951826 | Silicon carbide deposition for use as a low dielectric constant anti-reflective coating The present invention generally provides a process for depositing silicon carbide using a silane-based material with certain process parameters that is useful for forming a suitable ARC for IC applications. Under certain process parameters, a fixed thickness of the ... | 10/04/2005 |
| 6943088 | Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner roun... | 09/13/2005 |
| 6927115 | Method of fabricating semiconductor integrated circuit The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform bas... | 08/09/2005 |
| 6909150 | Mixed signal integrated circuit with improved isolation An integrated circuit having improved isolation includes a first circuit section formed in a substrate and a second circuit section formed in the substrate, the second circuit section being spaced laterally from the first circuit section. The integrated circuit furt... | 06/21/2005 |
| 6900108 | High temperature sensors utilizing doping controlled, dielectrically isolated beta silicon carbide (SiC) sensing elements on a specifically selected high temperature force collecting membrane Semiconductor devices useful in high temperature sensing applications include a silicon carbide substrate, a silicon dioxide layer, and an outer layer of crystalline doped silicon carbide. The device is a 3C—SiC/SiO2/SiC structure. This structure can be... | 05/31/2005 |
| 6867495 | Integrated circuit having a device wafer with a diffused doped backside layer Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the h... | 03/15/2005 |
| 6822325 | Isolating temperature sensitive components from heat sources in integrated circuits Temperature sensitive devices may be shielded from temperature generating devices on the same integrated circuit by appropriately providing a trench that thermally isolates the heat generating devices from the temperature sensitive devices. In one embodiment, the tr... | 11/23/2004 |
| 6815794 | Semiconductor devices with multiple isolation structure and methods for fabricating the same Semiconductor devices with a multiple isolation structure and methods for fabricating the same are provided. In one aspect, a semiconductor device comprises a heavily doped buried layer having a first conductivity type, which is formed in a predetermined region of a... | 11/09/2004 |
| 6787880 | ESD parasitic bipolar transistors with high resistivity regions in the collector A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions ... | 09/07/2004 |
| 6764922 | Method of formation of an oxynitride shallow trench isolation An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench li... | 07/20/2004 |
| 6759303 | Complementary vertical bipolar junction transistors fabricated of silicon-on-sapphire utilizing wide base PNP transistors A method for fabricating complementary vertical bipolar junction transistors of silicon-on-sapphire in fewer steps than required for true complimentary vertical bipolar junction transistors is disclosed. Initially a thin layer of silicon is grown on a sapphire subst... | 07/06/2004 |
| 6729886 | Method of fabricating a drain isolated LDMOS device A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are def... | 05/04/2004 |
| 6693325 | Semiconductor device having silicon on insulator and fabricating method therefor The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device... | 02/17/2004 |
| 6627515 | Method of fabricating a non-floating body device with enhanced performance A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semicondu... | 09/30/2003 |
| 6620654 | Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers includes forming a first doped and activated polysilicon area (either n-type or p-type) on a substrate. An isolation material layer is formed abutting the firs... | 09/16/2003 |
| 6589833 | ESD parasitic bipolar transistors with high resistivity regions in the collector A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silici... | 07/08/2003 |
| 6562694 | Method of manufacturing a semiconductor device comprising semiconductor elements formed in a toplayer of a silicon wafer situated on a buried insulating layer A method of manufacturing a semiconductor device including semiconductor elements having semiconductor zones (17, 18, 24, 44, 45) formed in a top layer (4) of a silicon wafer (1) situated on a buried insulating layer (2). In this method, a first series of... | 05/13/2003 |
| 6406976 | Semiconductor device and process for forming the same Semiconductor devices and processes for forming the same. The semiconductor device includes field isolation regions within trenches lying within a semiconductor device substrate. The trenches include a first trench and a second trench. The device includes... | 06/18/2002 |
| 6395593 | Method of manufacturing high side and low side guard rings for lowest parasitic performance in an H-bridge configuration A method of minimizing parasitics in an MOS device caused by the formation of a bipolar transistor within the MOS devices and the device, primarily for a polyphase bridge circuit. For the low side device, a substrate of a first conductivity type is provid... | 05/28/2002 |
| 6335230 | Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers wherein a first doped and activated polysilicon layer (either n-type and p-type) is patterned on a substrate. An isolation material layer is formed abutting th... | 01/01/2002 |
| 6331470 | Process for manufacturing a semiconductor material wafer having power regions dielectrically insulated from circuitry regions A manufacturing process is carried out starting from an SOI type wafer including a top silicon layer and a bottom silicon layer separated from each other by a buried silicon dioxide layer. In the top layer, a LOCOS type sacrificial region is formed and th... | 12/18/2001 |
