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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 7244644 | Undercut and residual spacer prevention for dual stressed layers Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer ov... | 07/17/2007 |
| 7190075 | Method of forming smooth polycrystalline silicon electrodes for molecular electronic devices A method is provided for forming smooth polycrystalline silicon electrodes for molecular electronic devices. The method comprises: depositing a silicon layer in an amorphous form; forming a native oxide on a surface of the amorphous silicon layer at a temperature be... | 03/13/2007 |
| 7135411 | Method for etching mesa isolation in antimony-based compound semiconductor structures Antimony-based semiconductor devices are formed over a substrate structure (10) that includes an antimony-based buffer layer (24) and an antimony-based buffer cap (26). Multiple epitaxial layers (30–42) formed over the substrate structu... | 11/14/2006 |
| 7101744 | Method for forming self-aligned, dual silicon nitride liner for CMOS devices A method for forming a self-aligned, dual silicon nitride liner for CMOS devices includes forming a first type nitride layer over a first polarity type device and a second polarity type device, and forming a topographic layer over the first type nitride layer. Porti... | 09/05/2006 |
| 7091082 | Semiconductor method and device A method for enhancing operation of a bipolar light-emitting transistor includes the following steps: providing a bipolar light-emitting transistor having emitter, base, and collector regions; providing electrodes for coupling electrical signals with the emitter, ba... | 08/15/2006 |
| 7060584 | Process to improve high performance capacitor properties in integrated MOS technology A method of fabricating a high performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition an... | 06/13/2006 |
| 6943088 | Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner roun... | 09/13/2005 |
| 6916740 | Method of forming smooth polycrystalline silicon electrodes for molecular electronic devices A method is provided for forming smooth polycrystalline silicon electrodes for molecular electronic devices. The method comprises: depositing a silicon layer in an amorphous form; forming a native oxide on a surface of the amorphous silicon layer at a temperature be... | 07/12/2005 |
| 6881639 | Method of manufacturing semiconductor device The present invention provides a method of manufacturing semiconductor devices, by which InGaAs-base C-top HBTs are manufactured at low cost. Helium ions with a smaller radius are implanted into a p-type InGaAs layer (in external base regions) not covered with a lam... | 04/19/2005 |
| 6872447 | Surface-protective pressure-sensitive adhesive sheet The pressure-sensitive adhesive sheet for surface protection has a three-layered film formed by laminating a layer A, a layer B and a layer C in this order and a pressure-sensitive adhesive layer formed on the layer C; wherein the layer A contains a polyethylene in ... | 03/29/2005 |
| 6828206 | Semiconductor device and method for fabricating the same In a method for fabricating a semiconductor device, a silicide material is formed at least on the surface of an area to be silicided. Then, a first RTA (Rapid Thermal Annealing) process is performed to form a first-reacted silicide region. Next, a supplemental silic... | 12/07/2004 |
| 6750109 | Halo-free non-rectifying contact on chip with halo source/drain diffusion A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion... | 06/15/2004 |
| 6541345 | Semiconductor device with SOI structure Disclosed is a semiconductor device including a SOI substrate having a SOI layer, in which a structure made from a semiconductor device is buried; a thick oxide film formed on the structure by selectively oxidizing the structure using as a mask an oxidati... | 04/01/2003 |
| 6458668 | Method for manufacturing hetero junction bipolar transistor Disclosed is a method for manufacturing a hetero junction bipolar transistor capable of forming a ledge by using a low-priced contact aligner and in a selective wet etching manner, without having any expensive stepper and dry etching and forming a ballast... | 10/01/2002 |
| 6395610 | Method of making bipolar transistor semiconductor device including graded, grown, high quality oxide layer A bipolar transistor includes an oxide layer having graded portions with greatly reduced stress on a silicon substrate. The method of making the oxide preferably includes growing a first oxide portion by upwardly ramping the silicon substrate to a first t... | 05/28/2002 |
| 6316815 | Structure for isolating integrated circuits in semiconductor substrate and method for making it A trench isolation structure characterized by a dielectric stud filling and spanning a trench in a semiconductor substrate is suggested for isolating the integrated circuits fabricated in the semiconductor substrate. The dielectric stud is formed by depos... | 11/13/2001 |
| 6218220 | Method for fabricating thin film transistor A method for fabricating a thin film transistor includes the steps of forming an active layer on a substrate, forming a metal gate electrode on the active layer, depositing a silicon layer on the metal gate electrode and the active layer, causing the meta... | 04/17/2001 |
| 6180483 | Structure and fabrication method for multiple crown capacitor A multiple crown capacitor and a method of fabricating such a capacitor is described. The method is applicable to a substrate in which an isolation layer is formed on the substrate, with a node contact plug formed in the isolation layer. A sacrificial lay... | 01/30/2001 |
| 5539301 | Monolithically integrated power output stage A monolithically integrated power output stage detects the load current through an output-stage transistor. Switch logic coupled to an output transistor is for switching the output transistor when a predetermined load-current threshold is reached. In this... | 07/23/1996 |
| 5399510 | Method of fabricating a semiconductor device In order to simplify the structure of a power amplifying transistor and improve its high-frequency characteristics, a base electrode (7b) and a collector electrode (7c) are formed on the surface of such a power amplifying transistor, while an emitter elec... | 03/21/1995 |
| 5145795 | Semiconductor device and method therefore An improved high frequency dielectrically isolated (DIC) transistor (100) or integrated circuit is obtained by providing a highly doped single crystal semiconductor region (112) coupled to the device reference terminal (16') and extending between front (9... | 09/08/1992 |
| 4949146 | Structured semiconductor body A structured semiconductor body e.g., an integrated circuit or a transistor, based on an silicon substrate having barrier regions which contain polycrystalline silicon, preferably produced by a silicon MBE process. The barrier regions are required to deli... | 08/14/1990 |
| 4283235 | Dielectric isolation using shallow oxide and polycrystalline silicon utilizing selective oxidation A process is described which combine polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a comb... | 08/11/1981 |
| 4231819 | Dielectric isolation method using shallow oxide and polycrystalline silicon utilizing a preliminary etching step A process is described which combines polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a com... | 11/04/1980 |
| 4184172 | Dielectric isolation using shallow oxide and polycrystalline silicon A process is described which combines polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a com... | 01/15/1980 |
