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| Number | Title | Issue Date |
| 6958621 | Method and circuit for element wearout recovery A recovery circuit and a method for employing the same are provided. The recovery circuit has a current driver and, preferably two pass-gates, a first pass-gate connected in series to the current driver and a second pass-gate connected to a ground. The recovery circ... | 10/25/2005 |
| 6432776 | Method of manufacturing semiconductor device A section separator region is formed in a semiconductor substrate in which a p-type well region has been formed, to separate the substrate into an I/O section and a core section. An oxide film and a plysilicon film are form at the I/O section, and pre-for... | 08/13/2002 |
| 6306692 | Coplanar type polysilicon thin film transistor and method of manufacturing the same The present invention discloses a method of manufacturing a thin film transistor, including: depositing an amorphous silicon layer, an insulating layer, and a gate metal layer on a substrate sequentially; patterning the insulating layer and the gate metal... | 10/23/2001 |
| 6165828 | Structure and method for gated lateral bipolar transistors An improved structure and method for gated lateral bipolar transistors is provided. The present invention capitalizes on opposing sidewall structures and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. ... | 12/26/2000 |
| 6143586 | Electrostatic protected substrate An electrostatic protected integrated circuit (IC) substrate and a method of making an integrated circuit package with the electrostatic protected IC substrate includes an IC substrate, having a plurality of electrical traces formed on the top of the IC s... | 11/07/2000 |
| 5856213 | Method of fabricating a programmable function system block using two masks and a sacrificial oxide layer between the bottom metal and an amorphous silicon antifuse structure An antifuse structure is formed between two metal contacts in which a thin oxide layer is formed on the first or bottom metal, a shallow via is provided oxide layer and a layer of amorphous silicon is deposited over the thin oxide and into the shallow via... | 01/05/1999 |
| 4910159 | Method for incrementally increasing the collector area of a lateral PNP transistor during electrical testing of an integrated device on wafer The collector area of a lateral PNP transistor may be incrementally increased during an electic testing step on wafer of an integrated circuit by purposely forming an auxiliary p-type diffused collector region having fractional dimensions near the primary... | 03/20/1990 |
| 4874711 | Method for altering characteristics of active semiconductor devices Method for altering an electrical characteristic of a circuit having at least one active semiconductor device involves applying at least one pulse--a voltage pulse, a current pulse, an energy pulse, or a power pulse and so forth--across the active semicon... | 10/17/1989 |
| 4569121 | Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing deposition of amorphous semiconductor layer In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islan... | 02/11/1986 |
| 4488349 | Method of repairing shorts in parallel connected vertical semiconductor devices by selective anodization A method of repairing shorts in parallel connected vertical semiconductor devices including a plurality of parallel-connected transistors comprises an anodizing step, before the electrodes are formed, in addition to the conventional manufacturing steps. S... | 12/18/1984 |
| 4403399 | Method of fabricating a vertical fuse utilizing epitaxial deposition and special masking In a memory array wherein each cell includes an emitter follower, a diode is formed on the emitter by a thin layer which is capable of being shorted by vertical migration of bit line atoms through the layer and into the emitter region. The thin layer is f... | 09/13/1983 |
| 3999282 | Method for manufacturing semiconductor devices having oxide films and the semiconductor devices manufactured thereby A silicon crystal body having a major surface lying parallel to a {110} or {100} crystal plane is prepared. A silicon oxide film is formed on the major surface by heating the body in an atmosphere containing steam. Then, an aluminum layer is formed on the... | 12/28/1976 |
