Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 7397070 | Self-aligned transistor In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor. ... | 07/08/2008 |
| 7358131 | Methods of forming SRAM constructions The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 04/15/2008 |
| 7300850 | Method of forming a self-aligned transistor In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor. ... | 11/27/2007 |
| 7199055 | Magnetic memory cell junction and method for forming a magnetic memory cell junction A method for patterning a magnetic memory cell junction is provided herein, which includes etching exposed portions of a stack of layers to a level spaced above a tunneling barrier layer of the stack of layers. In addition, the method may include implanting dopants ... | 04/03/2007 |
| 7180159 | Bipolar transistor having base over buried insulating and polycrystalline regions A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface l... | 02/20/2007 |
| 7153731 | Method of forming a field effect transistor with halo implant regions A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed withi... | 12/26/2006 |
| 7151035 | Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a... | 12/19/2006 |
| 7125785 | Mixed orientation and mixed material semiconductor-on-insulator wafer The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordanc... | 10/24/2006 |
| 7087979 | Bipolar transistor with an ultra small self-aligned polysilicon emitter The intrinsic base region of a bipolar transistor is formed to avoid a chemical interaction between the chemicals used in a chemical mechanical polishing step and the materials used to form the base region. The method includes the step of forming a trench in a layer... | 08/08/2006 |
| 7087959 | Metal-oxide-semiconductor device having an enhanced shielding structure An MOS device includes a semiconductor layer formed on a substrate, the substrate defining a horizontal plane and a vertical direction normal to the horizontal plane. First and second source/drain regions are formed in the semiconductor layer proximate an upper surf... | 08/08/2006 |
| 7008547 | Solid phase sensors Provided is a solid phase array of electrical sensors, each comprising a channel and electrical leads for attaching to a voltage, current or resistivity meter for measuring the voltage, current or resistivity through the pore, wherein the channels are formed of a si... | 03/07/2006 |
| 7005723 | Bipolar transistor and method of producing same In a method of producing a bipolar transistor, a semiconductor substrate having a substrate surface is provided. A base-terminal layer for providing a base terminal is formed on the substrate surface, and an emitter window having a wall area is formed in the base-te... | 02/28/2006 |
| 7002221 | Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silico... | 02/21/2006 |
| 6960820 | Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrins... | 11/01/2005 |
| 6949438 | Method of fabricating a bipolar junction transistor A substrate with a plurality of isolation structures for defining at least an active area thereon is provided. Ions of a first conductive type are implanted into the substrate to form a doping region in the active area. Following that, a protective layer is formed o... | 09/27/2005 |
| 6943428 | Semiconductor device including bipolar transistor and buried conductive region A semiconductor device and a method for manufacturing the device using a semiconductor substrate of a high resistance with improved Q value of a passive circuit element. Leakage current due to an impurity fluctuation, in the high resistance semiconductor substrate a... | 09/13/2005 |
| 6930010 | Method of forming a conductive structure in a semiconductor material A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bot... | 08/16/2005 |
| 6924202 | Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer a... | 08/02/2005 |
| 6911716 | Bipolar transistors with vertical structures A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequ... | 06/28/2005 |
| 6828649 | Semiconductor device having an interconnect that electrically connects a conductive material and a doped layer, and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one advantageous embodiment, the semiconductor device includes a doped layer located over a semiconductor substrate, and an isol... | 12/07/2004 |
| 6815304 | Silicon carbide bipolar junction transistor with overgrown base region Silicon carbide bipolar junction transistors having an overgrown base layer are provided. The bipolar junction transistors can be made with a very thin (e.g., 0.3 μm or less) base layer while still possessing adequate peripheral base resistance values. Self alignin... | 11/09/2004 |
| 6808999 | Method of making a bipolar transistor having a reduced base transit time A bipolar transistor has a high performance and high reliability, which are obtained by enhancing a withstanding voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, an opening dispose... | 10/26/2004 |
| 6797580 | Method for fabricating a bipolar transistor in a BiCMOS process and related structure According to one exemplary embodiment, a method for fabricating a bipolar transistor in a BiCMOS process comprises a step of forming an emitter window stack by sequentially depositing a base oxide layer and an antireflective coating layer on a top surface of a base,... | 09/28/2004 |
| 6753234 | Method of forming the silicon germanium base of a bipolar transistor The intrinsic base region of a bipolar transistor is formed to avoid a chemical interaction between the chemicals used in a chemical mechanical polishing step and the materials used to form the base region. The method includes the step of forming a trench in a layer... | 06/22/2004 |
| 6686250 | Method of forming self-aligned bipolar transistor A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emit... | 02/03/2004 |
| 6674146 | Composite dielectric layers An apparatus including a contact point on a substrate; a first dielectric layer comprising a material having a dielectric constant less than five formed on the contact point, and a different second dielectric layer formed on the substrate and separated fr... | 01/06/2004 |
| 6635545 | Method for fabricating a bipolar transistor and method for fabricating an integrated circuit configuration having such a bipolar transistor The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and betwe... | 10/21/2003 |
| 6597053 | Integrated circuit arrangement with a number of structural elements and method for the production thereof An integrated circuit arrangement having a number of structural elements, at least one of which is surrounded by a metallic shielding structure. This structural element is thus protected against interference due to disturbing impulses from its environment... | 07/22/2003 |
| 6579774 | Semiconductor device fabrication method A semiconductor device fabrication method includes the steps of forming a first insulation layer and a first semiconductor layer sequentially on a semiconductor substrate having a buried diffusion region therein. A second insulation layer is formed on the... | 06/17/2003 |
| 6573147 | Method of forming a semiconductor device having contact using crack-protecting layer A semiconductor device having a contact using a crack-protecting layer and a method of forming the same are provided. The crack-protecting layer formed of a dielectric material is formed on an interlayer dielectric layer. The crack-protecting layer reliev... | 06/03/2003 |
| 6506655 | Bipolar transistor manufacturing method A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an... | 01/14/2003 |
| 6492219 | High voltage shield An integrated circuit has a guard ring for shielding a first area 14 (eg. high voltage area) from a second area 15 (eg.low voltage). The guard ring comprises a conductive guard ring 6, (eg. metal), which is partially exposed through a passivation layer 13... | 12/10/2002 |
| 6482710 | Bipolar transistor and manufacting method thereof A bipolar transistor according to the invention is provided with structure that an intrinsic base made of single crystal Si--Ge and a base leading-out electrode are connected via a link base made of polycrystal Si--Ge by doping at high concentration, furt... | 11/19/2002 |
| 6432789 | Method of forming a well isolation bipolar transistor The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type ... | 08/13/2002 |
| 6429085 | Self-aligned non-selective thin-epi-base silicon germaniun (SiGe) heterojunction bipolar transistor BiCMOS process using silicon dioxide etchback A process used in the fabrication of a self-aligned non-selective thin-epi-base silicon germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS. The process involves using TEOS or Spin-On-Glass (SOG) silicon dioxide etchback in the fabrication of ... | 08/06/2002 |
| 6337251 | Method of manufacturing semiconductor device with no parasitic barrier In a method of manufacturing a semiconductor device, a first insulating film is formed on a semiconductor substrate, a first conductive film is formed on the first insulating film, and a second insulating film is formed on the first conductive film. An op... | 01/08/2002 |
| 6291304 | Method of fabricating a high voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device)d a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 09/18/2001 |
| 6258686 | Manufacturing method of semiconductor device and semiconductor device A manufacturing method of a bipolar transistor that can reduce, without increasing capacitance between base-collector, withstand voltage deterioration and leakage between emitter-base is provided. On an upper surface of an active area of a semiconductor s... | 07/10/2001 |
| 6235601 | Method of manufacturing a self-aligned vertical bipolar transistor A process is set forth for providing a self-aligned, vertical bipolar transistor. A controlled technique is provided for providing the base and emitter features of the transistor with appropriate dimensions and properties to be useful in high frequency mi... | 05/22/2001 |
| 6184102 | Method for manufacturing a well isolation bipolar transistor The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type ... | 02/06/2001 |
