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| Number | Title | Issue Date |
| 6773978 | Methods for improved metal gate fabrication Methods are disclosed for manufacturing semiconductor devices with silicide metal gates, wherein a single-step anneal is used to react a metal such as cobalt or nickel with substantially all of a polysilicon gate structure while source/drain regions are covered. A s... | 08/10/2004 |
| 6616786 | Process for applying an ink-only label to a polymeric surface The invention is directed to a returnable plastic crate provided on at least one surface with an ink only label that is removable without destructive treatment of the said surface, said label being adhered to said at least one surface by an activated adhe... | 09/09/2003 |
| 6420238 | Method of fabricating high-capacitance capacitive elements in a semiconductor substrate Described in the disclosure is a method for fabricating high-capacitance capacitive elements that are integrated in a semiconductor substrate. First a dielectric layer is formed over the surface of the substrate and a metal layer is deposited thereon. The... | 07/16/2002 |
| 4778772 | Method of manufacturing a bipolar transistor A method of manufacturing a semiconductor device by forming an N type collector layer in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains... | 10/18/1988 |
| 4667218 | NPN transistor with base double doped with arsenic and boron A semiconductor device comprising an N type collector layer formed in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity... | 05/19/1987 |
| 4263067 | Fabrication of transistors having specifically paired dopants A semiconductor device comprising an N type collector layer formed in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity... | 04/21/1981 |
| 4226650 | Method of reducing emitter dip in transistors utilizing specifically paired dopants A semiconductor device comprising an N type collector layer formed in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity... | 10/07/1980 |
| 4006046 | Method for compensating for emitter-push effect in the fabrication of transistors A semiconductor wafer having a base dopant source disposed on its surface receives a surface coating consisting of, for example, a silicon nitride film. An emitter opening is formed in the silicon nitride surface coating and a portion of the base dopant s... | 02/01/1977 |
