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| Number | Title | Issue Date |
| 7491617 | Transistor structure with minimized parasitics and method of fabricating the same A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrin... | 02/17/2009 |
| 7339254 | SOI substrate for integration of opto-electronics with SiGe BiCMOS According to an exemplary embodiment, a structure includes a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. The structure further includes a trench formed... | 03/04/2008 |
| 7338848 | Method for opto-electronic integration on a SOI substrate and related structure According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer... | 03/04/2008 |
| 7279769 | Semiconductor device and manufacturing method thereof To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an ele... | 10/09/2007 |
| 7233031 | Vertical power semiconductor component A vertical power semiconductor component, e.g. a diode or an IGBT, in which there are formed, on the rear side of a substrate, a rear side emitter or a cathode emitter and, over that, a rear side metal layer that at least partly covers the latter, is defined by the ... | 06/19/2007 |
| 7180159 | Bipolar transistor having base over buried insulating and polycrystalline regions A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface l... | 02/20/2007 |
| 7118982 | Emitter and method of making An emitter includes an electron source and a cathode. The cathode has an emissive surface. The emitter further includes a continuous anisotropic conductivity layer disposed between the electron source and the emissive surface of the cathode. The anisotropic conducti... | 10/10/2006 |
| 7098113 | Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accor... | 08/29/2006 |
| 7087925 | Semiconductor device having reduced capacitance to substrate and method In one embodiment, a matrix of free-standing semiconductor shapes are oxidized to form a low capacitance isolation tub. The adjacent rows of shapes in the matrix are offset with respect to each to minimize air gap and void formation during tub formation. In a furthe... | 08/08/2006 |
| 7087940 | Structure and method of forming bipolar transistor having a self-aligned raised extrinsic base using self-aligned etch stop layer A bipolar transistor structure and method of making the bipolar transistor are provided. The bipolar transistor includes a collector region, an intrinsic base layer overlying the collector region, and an emitter overlying the intrinsic base layer. An opened etch sto... | 08/08/2006 |
| 7063798 | Method for realizing microchannels in an integrated structure A process is presented for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2). The process forms in the substrate (2) at least one trench (4). A microchannel (10... | 06/20/2006 |
| 7042701 | High-voltage CMOS-compatible capacitors A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate having a first semiconductive body and a second plate having a floating electrode. The first and second semiconductive bodies are electrically i... | 05/09/2006 |
| 7026666 | Self-aligned NPN transistor with raised extrinsic base A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase i... | 04/11/2006 |
| 6933214 | Method of manufacturing flash memories of semiconductor devices Disclosed is a method of manufacturing a semiconductor device. A monoatomic dopant having a high atomic weight is implanted to form an ion implantation layer, instead of using a dopant of a small atomic weight such as B or a molecular ion such as a BF2 in... | 08/23/2005 |
| 6930010 | Method of forming a conductive structure in a semiconductor material A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bot... | 08/16/2005 |
| 6815801 | Vertical bipolar transistor and a method of manufacture therefor including two epitaxial layers and a buried layer The present invention provides a vertical bipolar transistor 110, a method of manufacture therefor, and an integrated circuit including the same. The vertical bipolar transistor 110 may include, in one embodiment, a second epitaxial layer 140 lo... | 11/09/2004 |
| 6784065 | Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small extrinsic emitter region reduces the maximum current that can flow throug... | 08/31/2004 |
| 6686250 | Method of forming self-aligned bipolar transistor A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emit... | 02/03/2004 |
| 6656812 | Vertical bipolar transistor having little low-frequency noise and high current gain, and corresponding fabrication process A vertical bipolar transistor includes a semiconductor substrate, an extrinsic collector layer in the semiconductor substrate, an intrinsic collector on the extrinsic collector, a lateral isolating region surrounding an upper part of the intrinsic collect... | 12/02/2003 |
| 6531369 | Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe) A Heterojunction Bipolar Transistor (HBT) is provided where the SiGe base region is formed through selective deposition, after the formation of the base electrode layer and the emitter window. A sacrificial oxide layer is deposited between the collector a... | 03/11/2003 |
| 6506655 | Bipolar transistor manufacturing method A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an... | 01/14/2003 |
| 6461926 | Circuit and method for a memory cell using reverse base current effect A memory cell is provided. The memory cell includes a field-effect transistor having a source region, a drain region and a gate coupled to a wordline. The memory cell also includes a vertical bipolar junction transistor that is biased for use of the rever... | 10/08/2002 |
| 6444536 | Method for fabricating bipolar transistors In accordance with the invention, a bipolar transistor is fabricated by disposing a sacrificial layer over the conventional semiconductor workpiece. The sacrificial layer is patterned into a stripe corresponding to the emitter stripe, and the base contact... | 09/03/2002 |
| 6440810 | Method in the fabrication of a silicon bipolar transistor In the fabrication of a silicon bipolar transistor, a method for forming base regions and for opening an emitter window is provided. A silicon substrate is provided with suitable device isolation. A first base region is formed in or on top of the substrat... | 08/27/2002 |
| 6432789 | Method of forming a well isolation bipolar transistor The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type ... | 08/13/2002 |
| 6362065 | Blocking of boron diffusion through the emitter-emitter poly interface in PNP HBTs through use of a SiC layer at the top of the emitter epi layer The present invention relates to a method of forming a bipolar transistor or a heterojunction bipolar transistor. The method comprises forming a collector region associated with a semiconductor substrate, and forming a base region base region over at leas... | 03/26/2002 |
| 6319743 | Method of making thin film piezoresistive sensor Semiconductor piezoresistive sensors are formed by a process using selective laser activation of a doped semiconductor surface. The substrate is a flexible membrane such as a diaphragm or bellows. A layer of insulative dielectric material is first applied... | 11/20/2001 |
| 6306695 | Modified source side inserted anti-type diffusion ESD protection device An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality o... | 10/23/2001 |
| 6277701 | Circuit and method for a memory cell using reverse base current effect A memory cell is provided. The memory cell includes a field-effect transistor having a source region, a drain region and a gate coupled to a wordline. The memory cell also includes a vertical bipolar junction transistor that is biased for use of the rever... | 08/21/2001 |
| 6184102 | Method for manufacturing a well isolation bipolar transistor The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type ... | 02/06/2001 |
| 6180442 | Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer... | 01/30/2001 |
| 6156594 | Fabrication of bipolar/CMOS integrated circuits and of a capacitor The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, ope... | 12/05/2000 |
| 6153488 | Method for producing semiconductor device, and semiconductor device produced by same A method for producing a semiconductor device including a bipolar transistor, has the steps of: forming an element isolating region in a major surface of a semiconductor substrate to define an element forming region to form a collector region in the eleme... | 11/28/2000 |
| 5928964 | System and method for anisotropic etching of silicon nitride A system and method is provided for anisotropically etching a silicon nitride layer (12) in an ion-assisted plasma reactor. A chuck (34) supports a photoresist layer (10), the silicon nitride layer (12), and a semiconductor water (14). A chuck temperature... | 07/27/1999 |
| 5899723 | Oblique implantation in forming base of bipolar transistor In fabricating a bipolar transistor, semiconductor dopant is introduced into a semiconductor body during a base doping operation to define a doped region, that forms a PN junction with adjoining semiconductor material and abuts a slanted sidewall of a fie... | 05/04/1999 |
| 5846868 | Method for forming a walled-emitter transistor An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substra... | 12/08/1998 |
| 5786222 | Method of manufacturing high performance bipolar transistors in a BiCMOS process A BiCMOS manufacturing process for fabricating an emitter of a bipolar transistor includes the steps of forming footings on a silicon substrate for prospectively bearing edges of the emitter, forming a polysilicon emitter having a medial portion overlying... | 07/28/1998 |
| 5733791 | Methods for fabrication of bipolar device having high ratio of emitter to base area A bipolar transistor is provided whose emitter surrounds the base. The transistor has in some embodiments a high ratio of the emitter area to the base area and low collector and emitter resistances. Further, a transistor is provided in which a collector c... | 03/31/1998 |
| 5605849 | Use of oblique implantation in forming base of bipolar transistor In fabricating a bipolar transistor, semiconductor dopant is introduced into a semiconductor body during a base doping operation to define a doped region, part of which constitutes a base region for the transistor. The base doping operation entails ion im... | 02/25/1997 |
| 5554543 | Process for fabricating bipolar junction transistor having reduced parasitic capacitance A process for fabricating a BJT device on a semiconductor substrate is disclosed. The substrate serves as the collector. The process comprises the steps of, first, forming a shielding layer over the designated location over the surface of the substrate fo... | 09/10/1996 |
